Background Calibration of Pipelined ADCs Via Decision Boundary Gap Estimation

被引:39
作者
Brooks, Lane [1 ]
Lee, Hae-Seung [1 ]
机构
[1] MIT, Dept Elect Engn & Comp Sci, Cambridge, MA 02139 USA
关键词
Adaptive digital background calibration; capacitor mismatch; finite opamp gain; pipelined analog-to-digital converter (ADC); static nonlinearity;
D O I
10.1109/TCSI.2008.925373
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A method of indirect background digital calibration of the dominant static nonlinearities in pipelined analog-to-digital converters (ADC) is presented. The method, called decision boundary gap estimation (DBGE), monitors the output of the ADC to estimate the size of code gaps that result at the decision boundaries of each stage. Code gaps result from such effects as capacitor mismatch, finite opamp gain, finite current source output impedance, comparator offset, and charge injection. DBGE does not require special calibration signals or additional analog hardware and can even reduce the performance requirements of the analog circuitry. The calibration is performed using the input signal and thus requires that the input signal exercise the codes in the vicinity of the decision boundaries of each stage. If it does not exercise these codes, then lack of calibration is less critical because the nonlinearities will not appear in the output signal. DBGE is simple and amenable to hardware and/or software implementations. Simulation results indicate DBGE is highly accurate, robust, and adaptive even in the presence of parameter drift and circuit noise.
引用
收藏
页码:2969 / 2979
页数:11
相关论文
共 27 条
[21]   A 13-b linear, 40-MS/s pipelined ADC with self-configured capacitor matching [J].
Ray, Sourja ;
Song, Bang-Sup .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (03) :463-474
[22]  
Shu TH, 1996, BCTM PROC, P189, DOI 10.1109/BIPOL.1996.554644
[23]   A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC [J].
Siragusa, E ;
Galton, I .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (12) :2126-2138
[24]   Gain error correction technique for pipelined analogue-to-digital converters [J].
Siragusa, EJ ;
Galton, I .
ELECTRONICS LETTERS, 2000, 36 (07) :617-618
[25]  
Song B.S., 1988, IEEE J SOLID-ST CIRC, V33, P1316
[26]   True background calibration technique for pipelined ADC [J].
Sonkusale, S ;
Van der Spiegel, J ;
Nagaraj, K .
ELECTRONICS LETTERS, 2000, 36 (09) :786-788
[27]   A 2.5-V, 12-b, 5-Msample/s pipelined CMOS ADC [J].
Yu, PC ;
Lee, HS .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (12) :1854-1861