A security-aware hardware scheduler for modern multi-core systems with hard real-time constraints

被引:1
作者
Norollah, Amin [1 ]
Beitollahi, Hakem [1 ]
Kazemi, Zahra [3 ]
Fazeli, Mahdi [2 ]
机构
[1] IUST, Comp Engn Dept, Tehran, Iran
[2] Halmstad Univ, Halmstad, Sweden
[3] Grenoble INP, LCIS Lab, Grenoble, France
关键词
Hardware accelerator; Sorting network; Hardware sorter; Parallel sorting; High performance; Resource Efficient; FPGA;
D O I
10.1016/j.micpro.2022.104716
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we propose an online security-aware hardware scheduler, the so-called Secure And Fast hardware Scheduler (SAFAS), for real-time task scheduling in multi-core systems in the presence of schedule-based side -channel attacks. To avoid such attacks and ensure that all tasks meet their deadlines, SAFAS schedules critical tasks and their replicas using a hardware-based strict Least Slack Time first (LST) algorithm independently while it independently schedules the non-critical tasks using a hardware-based EDF algorithm. SAFAS enhances the system performance and reduces the chance of side-channel attacks due to the different processing cores allocated to each task in each scheduling interval. The hardware scheduler operates independently and in parallel with the multi-core system and hides the scheduling characteristics from adversaries. The software -based Earliest Deadline First (EDF) algorithm is also used for schedulability tests and feasibility analysis of hard real-time periodic tasks to maximize the number of tasks scheduled successfully in the multi-core system. SAFAS has been synthesized and simulated on a Xilinx Vivado 2018.2 and implemented on a Spartan-7 FPGA chip. Our experimental results indicate that SAFAS increases the performance of the system by 4.8 times as compared to previous state-of-the-art hardware schedulers while guaranteeing that all critical tasks and their replicas meet their deadlines.
引用
收藏
页数:11
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