Modeling and Measurement of Power Supply Noise Effects on an Analog-to-Digital Converter Based on a Chip-PCB Hierarchical Power Distribution Network Analysis

In this paper, a model of power supply noise (PSN) effects on an analog-to-digital converter (ADC) in a hierarchical structure is proposed. The ADC performance is determined by not only on-chip characteristics but also off-chip characteristics. Therefore, chip-package-printed circuit board (PCB) coanalysis and comodeling are required to accurately evaluate the performance of the ADC. We propose the comodel which allows the estimation and analysis of PSN effects on the ADC including off-chip characteristic. The proposed model includes three separate submodels: a power distribution network (PDN) model from the power/ground of the PSN source to the ADC power/ground, an on-chip circuit model from the ADC power/ground to the ADC inputs, and an ADC behavioral model from the ADC inputs to the factor of the effective number of bits (ENOB), which is one of the ADC performance factors. By applying a segmentation method for the PDN model, an analytical model for the on-chip circuit model, and a MATLAB model for the ADC behavioral model, fast, precise, and broadband estimations of the PSN effects are achieved. To validate the proposed models, an ADC was fabricated by a 0.13-mu m CMOS process and wire bonded to the designed PCB. The ENOB of the ADC was measured by sweeping the PSN's frequency from 1 MHz up to 3 GHz, which was injected into the PCB to discover which noise frequency is critical to an ADC designed with a chip-PCB hierarchical structure. The results estimated by the proposed model correlated well with the cosimulated and measured results. The proposed modeling procedure saves the chip, package, and PCB designers time and computation resources to achieve high-quality analog devices or mixed-mode systems and provides an intuitive understanding of the noise effect.