Asymmetric Cascaded Multi-level Inverter: A Solution to Obtain High Number of Voltage Levels

被引：13

作者：

Banaei, M. R. ^{[1
]}

Salary, E. ^{[1
]}

机构：

[1] Azarbaijan Shahid Madani Univ, Fac Engn, Dept Elect Engn, Tabriz, Iran

来源：

JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY | 2013年 / 8卷 / 02期

关键词：

Voltage Levels; Asymmetric state; H-bridge cascaded; HARMONIC ELIMINATION; CONVERTERS; TOPOLOGY; STATCOM;

D O I：

10.5370/JEET.2013.8.2.316

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Multilevel inverters produce a staircase output voltage from DC voltage sources. Requiring great number of semiconductor switches is main disadvantage of multilevel inverters. The multilevel inverters can be divided in two groups: symmetric and asymmetric converters. The asymmetric multilevel inverters provide a large number of output steps without increasing the number of DC voltage sources and components. In this paper, a novel topology for multilevel converters is proposed using cascaded sub-multilevel Cells. This sub-multilevel converters can produce five levels of voltage. Four algorithms for determining the DC voltage sources magnitudes have been presented. Finally, in order to verify the theoretical issues, simulation is presented.

引用

页码：316 / 325

页数：10

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