Optimal design of single-photon sensor front-end electronics for fast-timing applications

In the study presented, we focus on the contribution of the front-end electronics to the single-photon time resolution, particularly for Silicon Photomultipliers. We investigate from a simple model for current sensing front-ends, the impact of parameters such as detector capacitance, parasitic inductance in the interconnection and input impedance (equivalent RLC network) in the slew-rate of the signal on one side, and the interaction of series and parallel noise with the detector capacitance on the other side. Design equations for optimum input impedance and optimum front-end bandwidth are proposed, as well as design criteria to discern between RC or RLC input network, since optimum parameters may differ depending on the sensor-ASIC interconnection: either multi-channel architectures where the ASIC inputs are wire bonded to standard Silicon Photomultipliers, or hybrid implementations with vertical 3D integration of sensor and front-end electronics. The later case can greatly exploit segmentation of large area detectors as a strategy to minimize the time jitter. The study presented highlights time jitter improvement using small Silicon Photomultipliers, proposing analytical expressions to estimate the minimum number of micro-cells sharing common readout electronics that minimize time jitter.