A 12-BIT 400-MS/s CURRENT-STEERING DAC WITH DEGLITCHING TECHNIQUE

被引:4
作者
Xue, Xiaobo [1 ]
Zhu, Xiaolei [1 ]
Shi, Qifeng [1 ]
He, Lenian [1 ]
机构
[1] Zhejiang Univ, Inst VLSI Design, Hangzhou 310027, Zhejiang, Peoples R China
关键词
Digital-to-analog converter; current-steering; glitch error; switch-driver structure; CMOS;
D O I
10.1142/S0218126614500042
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, a 12-bit current-steering digital-to-analog converter (DAC) employing a deglitching technique is proposed. The deglitching technique is realized by lowering the voltage swing of the control signal as well as by using a method of glitch counteraction (GC). A new switch-driver structure is designed to enable the effectiveness of the GC and provide sufficient driving capability under a low supply voltage. Moreover, the control signal's rise/fall asymmetry which increases the glitch error can be suppressed by using the proposed switch-driver structure. The 12-bit DAC is implemented in 180nm CMOS technology. The measurement results show that the spurious free dynamic range (SFDR) at low signal frequency is 78.8 dB, and it is higher than 70 dB up to 60MHz signal frequency at 400 MS/s. The measured INL and DNL are both less than +/- 0.6 LSB.
引用
收藏
页数:13
相关论文
共 10 条
[1]   Modeling of glitches due to rise/fall asymmetry in current-steering digital-to-analog converters [J].
Andersson, KO ;
Vesterbacka, M .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2005, 52 (11) :2265-2275
[2]   The analysis and improvement of a current-steering DAC's dynamic SFDR-III: The output-dependent delay differences [J].
Chen, Tao ;
Gielen, Georges .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2007, 54 (02) :268-279
[3]  
Doris K., 2005, Proc. Digest of Technical Papers Solid-State Circuits Conf. ISSCC. 2005 IEEE Int, P116
[4]  
Jen-Hung Chi, 2010, Proceedings of the 36th European Solid State Circuits Conference (ESSCIRC 2010), P222, DOI 10.1109/ESSCIRC.2010.5619889
[5]  
Lin C. H., 1998, IEEE J SOLID-ST CIRC, V33, P315
[6]   A 10-Bit 1.6-GS/s 27-mW Current-Steering D/A Converter With 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS [J].
Palmers, Pieter ;
Steyaert, Michiel S. J. .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57 (11) :2870-2879
[7]   A low-spurious low-power 12-bit 160-MS/s DAC in 90-nm CMOS for baseband wireless transmitter [J].
Seo, Dongwon ;
McAllister, Gene H. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (03) :486-495
[8]   A Low Cost Calibrated DAC for High-Resolution Video Display System [J].
Shen, Meng-Hung ;
Huang, Po-Chiun .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (09) :1743-1747
[9]   Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC [J].
Shen, Meng-Hung ;
Tsai, Jen-Huan ;
Huang, Po-Chiun .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2010, 57 (05) :369-373
[10]   A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter [J].
Van den Bosch, A ;
Borremans, MAF ;
Steyaert, MSJ ;
Sansen, W .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (03) :315-324