A Built-in-self-test Method for DCMs in Xilinx Virtex-4 FPGAs

This paper proposes a built-in-self-test method for DCMs in Xilinx Virtex-4 FPGAs. Built-in-self-test technique is widely used in FPGA functional test. However, it is not commonly used in the test for the Digital Clock Management (DCM) resources because it is quite straightforward to implement frequency measurement in Automatic Test Equipment (ATE). The ATE based method has two drawbacks, one is it requires an error threshold and therefore a minor error might be accepted, the other is the difficulty passing high frequency clock to ATE with signal integrity. The method proposed in this paper can detect the minor error by using the alignment feature of the output clocks of DCM. We also propose a frequency scanning mechanism that can test a set of frequency points in the output frequency range by a single FPGA configuration file.