Double edge triggered feedback flip-flop in sub 100nm technology

被引：2

作者：

Rasouli, S. H. ^{[1
]}

Amirabadi, A. ^{[1
]}

Seyedi, A. ^{[1
]}

Afkah-Kusha, A. ^{[1
]}

机构：

[1] Univ Tehran, ECE Dept, Nanoelect Ctr Excellence, Tehran, Iran

来源：

ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS | 2006年

关键词：

D O I：

10.1109/ASPDAC.2006.1594698

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a new flip-flop called Double-edge triggered Feedback Flip-Flop (DFFF) is proposed. The dynamic power consumption of DFFF is reduced by avoiding unnecessary internal node transition. The subthreshold current in the flip-flops is very low compared to other structures. Reducing the number of transistor in the stack and increasing the number of charge path leads to higher operational speed compared to others flip-flops. The simulation results show an improvement of 44% in the speed and 45% in the static leakage power.

引用

页码：297 / 302

页数：6

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