Requirements for ultra-thin-film devices and new materials for the CMOS roadmap

被引:55
作者
Fenouillet-Beranger, C
Skotnicki, T
Monfray, S
Carriere, N
Boeuf, F
机构
[1] CEA, LETI, F-38054 Grenoble, France
[2] ST Microelect, F-38921 Crolles, France
关键词
SOI; metal gates; strained silicon; short-channel effects; fully-depleted; BOX; DIBL; subthreshold slope;
D O I
10.1016/j.sse.2003.12.039
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
For the first time various devices architectures (bulk, SOI and SON) and process modules (metal gate, strained-Si channel) are compared in a consistent way using the same analytical tool. This analysis shows on one hand that the conventional bulk cannot match the requirements throughout the entire ITRS'01 roadmap, but on the other hand it gives clear guidelines on device architectures permitting to do so. In other words, this paper puts forward a device architecture roadmap and shows precisely which architectures, modules and materials will be needed at a given CMOS node. This message analysis may be of importance for semiconductor manufacturers, equipment makers and SOI wafer providers. (C) 2004 Elsevier Ltd. All rights reserved.
引用
收藏
页码:961 / 967
页数:7
相关论文
共 28 条
[1]  
[Anonymous], P 30 ESSDERC
[2]   The impact of device scaling and power supply change on CMOS gate performance [J].
Chen, K ;
Wann, HC ;
Ko, PK ;
Hu, CM .
IEEE ELECTRON DEVICE LETTERS, 1996, 17 (05) :202-204
[3]   Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs:: optimization of the device architecture [J].
Ernst, T ;
Tinella, C ;
Raynaud, C ;
Cristoloveanu, S .
SOLID-STATE ELECTRONICS, 2002, 46 (03) :373-378
[4]   UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect [J].
Fukasaku, K ;
Ono, A ;
Hirai, T ;
Yasuda, Y ;
Okada, N ;
Koyama, S ;
Tamura, T ;
Yamada, Y ;
Nakata, T ;
Yamana, M ;
Ikezawa, N ;
Matsuda, T ;
Arita, K ;
Nambu, H ;
Nishizawa, A ;
Nakabeppu, K ;
Nakamura, N .
2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2002, :64-65
[5]  
HUANG SF, 2001, IEDM, P237
[6]  
Josse E., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P661, DOI 10.1109/IEDM.1999.824239
[7]   Silicon-on-nothing (SON) - an innovative process for advanced CMOS [J].
Jurczak, M ;
Skotnicki, T ;
Paoli, M ;
Tormen, B ;
Martins, J ;
Regolini, JL ;
Dutartre, D ;
Ribot, P ;
Lenoble, D ;
Pantel, R ;
Monfray, S .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (11) :2179-2187
[8]   Buried layer engineering to reduce the drain-induced barrier lowering of sub-0.05 μm SOI-MOSFET [J].
Koh, R .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1999, 38 (4B) :2294-2299
[9]  
Luyken R, 2002, 2002 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, P137, DOI 10.1109/SOI.2002.1044450
[10]   60nm gate length dual-Vt CMOS for high performance applications [J].
Mehrotra, M ;
Wu, J ;
Jain, A ;
Laaksonen, T ;
Kim, K ;
Bather, W ;
Koshy, R ;
Chen, J ;
Jacobs, J ;
Ukraintsev, V ;
Olsen, L ;
DeLoach, J ;
Mehigan, J ;
Agarwal, R ;
Walsh, S ;
Sekel, D ;
Tsung, L ;
Vaidyanathan, M ;
Trentman, B ;
Liu, K ;
Aur, S ;
Khamankar, R ;
Nicollian, P ;
Jiang, Q ;
Xu, Y ;
Campbell, B ;
Tiner, P ;
Wise, R ;
Scott, D ;
Rodder, M .
2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2002, :124-125