共 28 条
[1]
[Anonymous], P 30 ESSDERC
[4]
UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect
[J].
2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS,
2002,
:64-65
[5]
HUANG SF, 2001, IEDM, P237
[6]
Josse E., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P661, DOI 10.1109/IEDM.1999.824239
[8]
Buried layer engineering to reduce the drain-induced barrier lowering of sub-0.05 μm SOI-MOSFET
[J].
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS,
1999, 38 (4B)
:2294-2299
[9]
Luyken R, 2002, 2002 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, P137, DOI 10.1109/SOI.2002.1044450
[10]
60nm gate length dual-Vt CMOS for high performance applications
[J].
2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS,
2002,
:124-125