A 16 channel high resolution (<11 ps RMS) Time-to-Digital Converter in a Field Programmable Gate Array

被引：35

作者：

Ugur, C. ^{[1
]}

Bayer, E. ^{[2
]}

Kurz, N. ^{[3
]}

Traxler, M. ^{[3
]}

机构：

[1] Johannes Gutenberg Univ Mainz, Helmholtz Inst Mainz, D-55128 Mainz, Germany

[2] Univ Kassel, Digital Technol Grp, D-34121 Kassel, Germany

[3] GSI Helmholtz Ctr Heavy Ion Res, D-64291 Darmstadt, Germany

来源：

JOURNAL OF INSTRUMENTATION | 2012年 / 7卷

关键词：

Front-end electronics for detector readout; Digital electronic circuits; TRIGGER;

D O I：

10.1088/1748-0221/7/02/C02004

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

A 16-channel Time-to-Digital Converter (TDC) was implemented in a general purpose Field-Programmable Gate Array (FPGA). The fine time calculations are achieved by using the dedicated carry-chain lines. The coarse counter defines the coarse time stamp. In order to overcome the negative effects of temperature and power supply dependency bin-by-bin calibration is applied. The time interval measurements are done using 2 channels. The time resolution of channels are calculated for 1 clock cycle and a minimum of 10.3 ps RMS on two channels, yielding 7.3 ps RMS (10.3 ps/root 2) on a single channel is achieved.

引用

页数：9

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A 16 channel high resolution (&lt;11 ps RMS) Time-to-Digital Converter in a Field Programmable Gate Array

A 16 channel high resolution (<11 ps RMS) Time-to-Digital Converter in a Field Programmable Gate Array