A quantized analog delay for an ir-UWB Quadrature Downconversion Autocorrelation Receiver

A quantized analog delay is designed as a requirement for the autocorrelation function in the Quadrature Downconversion Autocorrelation Receiver (QDAR) [1]. The quantized analog delay is comprised of a quantizer, multiple binary delay fines and an adder circuit. Being the foremost element, the quantizer consists of a series of comparators, each one comparing the input signal to a unique reference voltage. The comparator outputs connect to binary delay lines, which are a cascade of synchronized D-latches. The outputs available at each line are linked together to reconstruct the incoming signal using an adder circuit. For a delay time of 550 ps, simulation results in IBM's CMOS 0.12 mu m technology show that the quantized analog delay requires a total current of 36.7 mA at a 1.6 V power supply. Furthermore, delays in the range of several nanoseconds are feasible at the expense of power. After a Monte Carlo simulation it becomes evident that the response of the quantized analog delay does not suffer drastically from neither process nor component mismatch variations.