Adjacent Common Centroid Placement for Analog IC Layout Design

被引:0
作者
Murotatsu, Kenichiro [1 ]
Fujiyoshi, Kunihiro [1 ]
机构
[1] Tokyo Univ Agr & Technol, Dept Elect & Elect Engn, Fuchu, Tokyo 183, Japan
来源
2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) | 2014年
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
To improve immunity against process gradients, common centroid constraint, in which every pair of elements should be placed symmetrically with respect to a common center point, is widely used. Several methods to obtain a good placement satisfying the constraint by using sequence-pair and Simulated Annealing were proposed. However, cells in a common centroid group should be placed close to the common center point of the group. In this paper, we propose methods which use mathematical-programming and can place cells in each group close to the common center point, and check the effectiveness of the methods by experimental comparisons.
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收藏
页码:619 / 622
页数:4
相关论文
共 14 条
  • [1] Asano S., 2010, P SASIMI2010, P243
  • [2] Fujiyoshi K, 2014, MIDWEST SYMP CIRCUIT, P226, DOI 10.1109/MWSCAS.2014.6908393
  • [3] Corner block list: An effective and efficient topological representation of non-slicing floorplan
    Hong, XL
    Huang, G
    Cai, YC
    Gu, JC
    Dong, SQ
    Cheng, CK
    Gu, J
    [J]. ICCAD - 2000 : IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, 2000, : 8 - 12
  • [4] KANEKO M, 1993, 1993 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS : PROCEEDINGS, VOLS 1-4 ( ISCAS 93 ), P2094, DOI 10.1109/ISCAS.1993.394169
  • [5] A linear programming-based algorithm for floorplanning in VLSI design
    Kim, JG
    Kim, YD
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2003, 22 (05) : 584 - 592
  • [6] Lin CW, 2011, DES AUT CON, P528
  • [7] Analog placement with common centroid constraints
    Ma, Qiang
    Young, Evangeline F. Y.
    Pun, K. P.
    [J]. IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2, 2007, : 579 - +
  • [8] SYSTEMATIC CAPACITANCE MATCHING ERRORS AND CORRECTIVE LAYOUT PROCEDURES
    MCNUTT, MJ
    LEMARQUIS, S
    DUNKLEY, JL
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (05) : 611 - 616
  • [9] Murata H, 1995, 1995 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, P472, DOI 10.1109/ICCAD.1995.480159
  • [10] RANDOM ERROR EFFECTS IN MATCHED MOS CAPACITORS AND CURRENT SOURCES
    SHYU, JB
    TEMES, GC
    KRUMMENACHER, F
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (06) : 948 - 955