20 GHz operation of an asynchronous wave-pipelined RSFQ arithmetic-logic unit

被引：81

作者：

Filippov, Timur V. ^{[1
]}

Sahu, Anubhav ^{[1
]}

Kirichenko, Alex F. ^{[1
]}

Vernik, Igor V. ^{[1
]}

Dorojevets, Mikhail ^{[2
]}

Ayala, Christopher L. ^{[2
]}

Mukhanov, Oleg A. ^{[1
]}

机构：

[1] HYPRES Inc, 175 Clearbrook Rd, Elmsford, NY 10523 USA

[2] SUNY Stony Brook, Dept Elect & Comp Engn, Stony Brook, NY 11794 USA

来源：

SUPERCONDUCTIVITY CENTENNIAL CONFERENCE 2011 | 2012年 / 36卷

关键词：

RSFQ; ALU; microprocessor; datapath; SINGLE FLUX; MICROPROCESSOR; DESIGN;

D O I：

10.1016/j.phpro.2012.06.130

中图分类号：

O412 [相对论、场论]; O572.2 [粒子物理学];

学科分类号：

摘要：

We have designed and tested at high frequency an RSFQ-based Arithmetic-Logic Unit (ALU), the critical component of an 8-bit RSFQ processor datapath. The ALU design is based on a Kogge-Stone adder and employs an asynchronous wave-pipelined approach scalable for wide datapath processors. The 8-bit ALU circuit was fabricated with HYPRES' standard 4.5 kA/cm(2) process and consists of 7,950 Josephson junctions, including input and output interfaces. In this paper, we present chip design and high-speed test results for the 8-bit ALU circuit. (C) 2012 Published by Elsevier B.V. Selection and/or peer-review under responsibility of the Guest Editors.

引用

页码：59 / 65

页数：7

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