FPGA-based area-efficient specific radar signal processor

被引：0

作者：

Chen, H ^{[1
]}

Liu, M ^{[1
]}

Han, YQ ^{[1
]}

机构：

[1] Beijing Inst Technol, Dept Elect Engn, Beijing 100081, Peoples R China

来源：

PROCEEDINGS OF THE 8TH JOINT CONFERENCE ON INFORMATION SCIENCES, VOLS 1-3 | 2005年

关键词：

radar signal processor; FPGA; FFT; hardware sharing;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper outlines the design techniques that have been applied to the development of a flexible processor which is used to perform high speed, real time signal processing applicable to one measuring radar. The core structure of this processor is one modified 512-point FFT which can also perform other signal processing operations by design reuse technology. The design applies the method of pipeline and block floating algorithm. It not only improves the processing speed but also precision.

引用

页码：408 / 411

页数：4

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