An Envelope Type (E-Type) Module: Asymmetric Multilevel Inverters With Reduced Components

被引:246
作者
Samadaei, Emad [1 ]
Gholamian, Sayyed Asghar [1 ]
Sheikholeslami, Abdolreza [1 ]
Adabi, Jafar [1 ]
机构
[1] Babol Noshirvani Univ Technol, Dept Comp & Elect Engn, Babol Sar 4714871167, Iran
关键词
Asymmetric; components; E-type; multilevel inverters (MLIs); power electronics; selective harmonics elimination (SHE); NUMBER; TOPOLOGY; PWM; CONVERTER;
D O I
10.1109/TIE.2016.2520913
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a new E-type module for asymmetrical multilevel inverters (MLIs) with reduced components. Each module produces 13 levels with four unequal dc sources and 10 switches. The design of the proposed module makes some preferable features with a better quality than similar modules such as the low number of semiconductors and dc sources and low switching frequency. Also, this module is able to create a negative level without any additional circuit such as an H-bridge, which causes reduction of voltage stress on switches. Cascade connection of the proposed structure leads to a modular topology with more levels and higher voltages. Selective harmonics elimination pulse width modulation (SHE-PWM) scheme is used to achieve high-quality output voltage with lower harmonics. MATLAB simulations and practical results are presented to validate the proposed module good performance. Module output voltage satisfies harmonics standard (IEEE519) without any filter in output.
引用
收藏
页码:7148 / 7156
页数:9
相关论文
共 22 条
[1]   New hybrid structure for multilevel inverter with fewer number of components for high-voltage levels [J].
Alishah, Rasoul Shalchi ;
Nazarpour, Daryoosh ;
Hosseini, Seyyed Hossein ;
Sabahi, Mehran .
IET POWER ELECTRONICS, 2014, 7 (01) :96-104
[2]   Extended multilevel converters: an attempt to reduce the number of independent DC voltage sources in cascaded multilevel converters [J].
Babaei, Ebrahim ;
Kangarlu, Mohammad Farhadi ;
Sabahi, Mehran .
IET POWER ELECTRONICS, 2014, 7 (01) :157-166
[3]   New cascaded multilevel inverter topology with minimum number of switches [J].
Babaei, Ebrahim ;
Hosseini, Seyed Hossein .
ENERGY CONVERSION AND MANAGEMENT, 2009, 50 (11) :2761-2767
[4]   A Review of Multilevel Selective Harmonic Elimination PWM: Formulations, Solving Algorithms, Implementation and Applications [J].
Dahidah, Mohamed S. A. ;
Konstantinou, Georgios ;
Agelidis, Vassilios G. .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2015, 30 (08) :4091-4106
[5]   A Hybrid Modular Multilevel Voltage Source Converter for HVDC Power Transmission [J].
Feldman, Ralph ;
Tomasini, Matteo ;
Amankwah, Emmanuel ;
Clare, Jon C. ;
Wheeler, Patrick W. ;
Trainer, David R. ;
Whitehouse, Robert S. .
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 2013, 49 (04) :1577-1588
[6]   Topology for multilevel inverters to attain maximum number of levels from given DC sources [J].
Gupta, K. K. ;
Jain, S. .
IET POWER ELECTRONICS, 2012, 5 (04) :435-446
[7]   Multilevel Inverter Topologies With Reduced Device Count: A Review [J].
Gupta, Krishna Kumar ;
Ranjan, Alekh ;
Bhatnagar, Pallavee ;
Sahu, Lalit Kumar ;
Jain, Shailendra .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2016, 31 (01) :135-151
[8]   Cross-switched multilevel inverter: an innovative topology [J].
Kangarlu, Mohammad Farhadi ;
Babaei, Ebrahim .
IET POWER ELECTRONICS, 2013, 6 (04) :642-651
[9]   A Generalized Cascaded Multilevel Inverter Using Series Connection of Submultilevel Inverters [J].
Kangarlu, Mohammad Farhadi ;
Babaei, Ebrahim .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2013, 28 (02) :625-636
[10]   Multilevel selective harmonic elimination PWM technique in series-connected voltage inverters [J].
Li, L ;
Czarkowski, D ;
Liu, YG ;
Pillay, P .
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 2000, 36 (01) :160-170