Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si

被引:87
作者
Kim, Jang Hyun [1 ]
Kim, Sangwan [2 ]
Park, Byung-Gook [1 ]
机构
[1] Seoul Natl Univ, Interuniv Semicond Res Ctr, Dept Elect & Comp Engn, Seoul 08826, South Korea
[2] Ajou Univ, Dept Elect & Comp Engn, Suwon 16499, South Korea
关键词
Bulk Si substrate; double-gate structure; low-power device; subthreshold swing (SS); tunnel field-effect transistor (TFET); vertical tunnel; FIELD-EFFECT TRANSISTORS; TUNNEL FET; SUBTHRESHOLD; N-2;
D O I
10.1109/TED.2019.2899206
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper examines a tunnel field-effect transistor (TFET) as a promising device for achieving steeper switching and better electrical performances in low-power operation. It features a double-gate TFET with vertical channel sandwiched by lightly doped Si (VS-TFET). The vertical tunnel junction is employed on the source side for the steeper subthreshold swing (SS) and for the higher ON-current (I-ON) by restricting tunnel barrier width. The VS-TFET shows 17-mV/decminimum SS and 10(4) ON/OFF current ratio (I-ON/I-OFF) for sub-0.7-V gate overdrive. In addition, the VS-TFET shows sub-60-mV/dec SS in a wide range of ID regardless of sweep directions. In conclusion, the work presented here demonstrates that the VS-TFET will be one of the most promising candidates for a next-generation low-power device.
引用
收藏
页码:1656 / 1661
页数:6
相关论文
共 37 条
[1]  
[Anonymous], 2009, EXPT DEMONSTRATION 1, DOI DOI 10.1109/IEDM.2009.5424355
[2]  
Auth C., 2017, INT EL DEVICES MEET, DOI DOI 10.1109/IEDM.2017.8268472
[3]  
Blaeser S, 2015, in Proc. Int. Electron. Devices Meeting, DOI 10.1109/IEDM.2015.7409757
[4]   Improved Subthreshold and Output Characteristics of Source-Pocket Si Tunnel FET by the Application of Laser Annealing [J].
Chang, Hsu-Yu ;
Adams, Bruce ;
Chien, Po-Yen ;
Li, Jiping ;
Woo, Jason C. S. .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (01) :92-96
[5]   Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires [J].
Chen, Z. X. ;
Yu, H. Y. ;
Singh, N. ;
Shen, N. S. ;
Sayanthan, R. D. ;
Lo, G. Q. ;
Kwong, D. -L. .
IEEE ELECTRON DEVICE LETTERS, 2009, 30 (07) :754-756
[6]   Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec [J].
Choi, Woo Young ;
Park, Byung-Gook ;
Lee, Jong Duk ;
Liu, Tsu-Jae King .
IEEE ELECTRON DEVICE LETTERS, 2007, 28 (08) :743-745
[7]   Subthreshold swing minimization of cylindrical tunnel FET using binary metal alloy gate [J].
Dash, Sidhartha ;
Sahoo, Girija Shankar ;
Mishra, Guru Prasad .
SUPERLATTICES AND MICROSTRUCTURES, 2016, 91 :105-111
[8]   Silicon Tunneling Field-Effect Transistors With Tunneling in Line With the Gate Field [J].
Fischer, Inga A. ;
Bakibillah, A. S. M. ;
Golve, Murali ;
Haehnel, Daniel ;
Isemann, Heike ;
Kottantharayil, Anil ;
Oehme, Michael ;
Schulze, Joerg .
IEEE ELECTRON DEVICE LETTERS, 2013, 34 (02) :154-156
[9]   CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With ≤ 50-mV/decade Subthreshold Swing [J].
Gandhi, Ramanathan ;
Chen, Zhixian ;
Singh, Navab ;
Banerjee, Kaustav ;
Lee, Sungjoo .
IEEE ELECTRON DEVICE LETTERS, 2011, 32 (11) :1504-1506
[10]   Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (≤ 50 mV/decade) at Room Temperature [J].
Gandhi, Ramanathan ;
Chen, Zhixian ;
Singh, Navab ;
Banerjee, Kaustav ;
Lee, Sungjoo .
IEEE ELECTRON DEVICE LETTERS, 2011, 32 (04) :437-439