Interface optimization for poly silicon/tungsten gates

被引：4

作者：

Schmidbauer, Sven ^{[1
]}

Hahn, Jens ^{[1
]}

Buerke, Axel ^{[1
]}

Jakubowski, Frank ^{[1
]}

Storbeck, Olaf ^{[1
]}

Ting, Yu-Wei

Schuster, Thomas ^{[1
]}

Faul, Juergen ^{[1
]}

机构：

[1] Qimonda Dresden GmbH & Co OHG, D-01099 Dresden, Germany

来源：

MICROELECTRONIC ENGINEERING | 2008年 / 85卷 / 10期

关键词：

Gate stack; Interface resistance; PVD; Sputtering; GC;

D O I：

10.1016/j.mee.2008.07.010

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Novel dual work function (DWF) based transistors featuring low gate resistances are presented. The process discussed enables extremely fast array timings easily and is thus key to fulfilling the performance requirements for high performance DRAM chips. The key enabler of the advanced gate integration scheme and its properties is the understanding of tuning the interface contact resistance. The objective of this work was to systematically investigate the role of the interface between poly-Si and metal of DRAM gate structures focused on electrical data. Contact resistance values, speed and elemental analysis information summarize the main findings of the gate development and furthermore the stable control of the very thin film stack in high volume production. (c) 2008 Elsevier B.V. All rights reserved.

引用

页码：2037 / 2041

页数：5

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