Replacing Copper Interconnects with Graphene at a 7-nm Node

We examine graphene for interconnects within a 7-nm FinFET technology. Multiple scenarios considered alter dimensions and/or materials to reflect realistic graphene interconnect fabrication. Replacement is restricted up to the 3rd BEOL metal layer (M3) as graphene is advantageous over copper in terms of resistivity only for line widths < 30 nm. Initial standard-cell level analysis is extended to benchmarking of a commercial 32-bit processor for the most promising graphene interconnect scenario: horizontally oriented graphene interconnects with bulk resistivity (rho(0)) of 1.5 mu Omega-cm and stack height (h) of 20 nm. Full-chip energy-delay-product (EDP) improves up to similar to 8% as the shorter graphene stack height reduces parasitic capacitances. We also consider the impact of graphene contact resistance on via resistances: although via resistance increases as much as 20x, low performance targets still demonstrate EDP improvement, suggesting further potential improvement from electronic design automation (EDA) tool optimization.