UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine

被引:23
作者
Li, Wuxi [1 ]
Lin, Yibo [1 ]
Li, Meng [1 ]
Dhar, Shounak [1 ]
Pan, David Z. [1 ]
机构
[1] Univ Texas Austin, Dept Elect & Comp Engn, EER, 2501 Speedway,C0803, Austin, TX 78712 USA
关键词
FPGA; placement; packing; clock legalization;
D O I
10.1145/3174849
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Modern field-programmable gate array (FPGA) devices contain complex clock architectures on top of configurable logics. Unlike application specific integrated circuits (ASICs), the physical structure of clock networks in an FPGA is pre-manufactured and cannot be adjusted to different applications. Furthermore, clock routing resources are typically limited for high-utilization designs. Consequently, clock architectures impose extra clock constraints and further complicate physical implementation tasks such as placement. Traditional ASIC placement techniques only optimize conventional design metrics such as wirelength, routability, power, and timing without clock legality consideration. It is imperative to have newtechniques to honor clock constraints during placement for FPGAs. In this article, we propose a high-performance FPGA placement engine, UTPlaceF 2.0, that optimizes wirelength and routability while honoring complex clock constraints. Our proposed approaches consist of an iterative minimum-cost-flow-based cell assignment as well as a clock-aware packing for producing clock-legal yet high-quality placement solutions. UTPlaceF 2.0 won first place in the ISPD' 17 clock-aware FPGA placement contest organized by Xilinx, outperforming the second- and the third-place winners by 4.0% and 10.0%, respectively, in routed wirelength with competitive runtime, on a set of industry benchmarks.
引用
收藏
页数:23
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