Scaling challenge of Self-Aligned STI cell (SA-STI cell) for NAND flash memories

被引:9
作者
Aritome, Seiichi [1 ,2 ]
Kikkawa, Takamaro [2 ]
机构
[1] SK Hynix Inc, R&D Div, Inchon 467701, Gyeonggi Do, South Korea
[2] Hiroshima Univ, Grad Sch Adv Sci Matter, Res Inst Nanodevice & Bio Syst, Hiroshima 730, Japan
关键词
Floating Gate; NAND; Flash memory; Scaling; INTERFERENCE; ARCHITECTURE; TECHNOLOGY; ACCURACY;
D O I
10.1016/j.sse.2013.01.006
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper describes scaling limitations and challenges of Self-Aligned STI cell (SA-STI cell) over 2X-OX nm generations for NAND flash memories. The scaling challenges are categorized to (1) narrow Read Window Margin (RWM) problem, (2) structural challenge, and (3) high field (5-10 MV/cm) problem. First, (1) the narrow RWM is investigated by extrapolating physical phenomena of FG-FG coupling interference, Electron Injection Spread (EIS), Back Pattern Dependence (BPD), and Random Telegraph Noise (RTN). The RWM is degraded not only by increasing programmed Vt distribution width, but also by increasing Vt of erase state mainly due to large FG-FG coupling interference. However, RWM is still positive in 1Z nm (10 nm) generation with 60% reduction of FG-FG coupling by air-gap process. For (2) structural challenge, the Control Gate (CG) fabrication margin between Floating Gates (FGs) is becoming much severer beyond 1X nm generation. Very narrow 5 nm FG width/space has to be controlled. For (3) high field problem, high field between CGs (word lines; WLs) is critical during program. By using WL air-gap, high field problem can be mitigated, and 1Y/1Z nm generation seems to be realized. Therefore, the SA-STI cell is expected to be able to scale down to 1Z nm (10 nm) generation, with the air gap of 60% reduced FG-FG coupling interference and an accurate control of FG/CG formation process. (C) 2013 Elsevier Ltd. All rights reserved.
引用
收藏
页码:54 / 62
页数:9
相关论文
共 35 条
[1]  
[Anonymous], IEEE EL DEV M WASH D, DOI DOI 10.1109/IEDM.2011.6131518
[2]   Advanced flash memory technology and trends for file storage application [J].
Aritome, S .
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :763-766
[3]  
ARITOME S, 1994, INTERNATIONAL ELECTRON DEVICES MEETING 1994 - IEDM TECHNICAL DIGEST, P61, DOI 10.1109/IEDM.1994.383466
[4]   AN ADVANCED NAND-STRUCTURE CELL TECHNOLOGY FOR RELIABLE 3.3-V-64 MB ELECTRICALLY ERASABLE AND PROGRAMMABLE READ ONLY MEMORIES (EEPROMS) [J].
ARITOME, S ;
HATAKEYAMA, I ;
ENDOH, T ;
YAMAGUCHI, T ;
SHUTO, S ;
IIZUKA, H ;
MARUYAMA, T ;
WATANABE, H ;
HEMINK, G ;
SAKUI, K ;
TANAKA, T ;
MOMODOMI, M ;
SHIROTA, R .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1994, 33 (1B) :524-528
[5]   Novel Negative Vt Shift Phenomenon of Program-Inhibit Cell in 2X-3X-nm Self-Aligned STI NAND Flash Memory [J].
Aritome, Seiichi ;
Seo, Soonok ;
Kim, Hyung-Seok ;
Park, Sung-Kye ;
Lee, Seok-Kiu ;
Hong, Sungjoo .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (11) :2950-2955
[6]   A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology [J].
Cernea, Raul-Adrian ;
Pham, Long ;
Moogat, Farookh ;
Chan, Siu ;
Le, Binh ;
Li, Yan ;
Tsao, Shouchang ;
Tseng, Tai-Yuan ;
Nguyen, Khanh ;
Li, Jason ;
Hu, Jayson ;
Yuh, Jong Hak ;
Hsu, Cynthia ;
Zhang, Fanglin ;
Kamei, Teruhiko ;
Nasu, Hiroaki ;
Kliza, Phil ;
Htoo, Khin ;
Lutze, Jeffrey ;
Dong, Yingda ;
Higashitani, Masaaki ;
Yang, Junnhui ;
Lin, Hung-Szu ;
Sakhamuri, Vamshi ;
Li, Alan ;
Pan, Feng ;
Yadala, Sridhar ;
Taigor, Subodh ;
Pradhan, Kishan ;
Lan, James ;
Chan, James ;
Abe, Takumi ;
Fukuda, Yasuyuki ;
Mukai, Hideo ;
Kawakami, Koichi ;
Liang, Connie ;
Ip, Tommy ;
Chang, Shu-Fen ;
Lakshmipathi, Jaggi ;
Huynh, Sharon ;
Pantelakis, Dimitris ;
Mofidi, Mehrdad ;
Quader, Khandker .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (01) :186-194
[7]   First evidence for injection statistics accuracy limitations in NAND Flash constant-current Fowler-Nordheim programming [J].
Compagnoni, C. Monzio ;
Spinelli, A. S. ;
Gusmeroli, R. ;
Lacaita, A. L. ;
Beltrami, S. ;
Ghetti, A. ;
Visconti, A. .
2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, :165-+
[8]   Ultimate Accuracy for the NAND Flash Program Algorithm Due to the Electron Injection Statistics [J].
Compagnoni, Christian Monzio ;
Spinelli, Alessandro S. ;
Gusmeroli, Riccardo ;
Beltrami, Silvia ;
Ghetti, Andrea ;
Visconti, Angelo .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (10) :2695-2702
[9]  
Daeyeal Lee, 2012, 2012 IEEE International Solid-State Circuits Conference (ISSCC), P430, DOI 10.1109/ISSCC.2012.6177077
[10]   Random telegraph noise in flash memories - Model and technology scaling [J].
Fukuda, Koichi ;
Shimizu, Yuui ;
Amemiya, Kazumi ;
Kamoshida, Masahiro ;
Hu, Chenming .
2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, :169-+