Concurrent error detection for finite state machines implemented with embedded memory blocks of SRAM-based FPGAs

被引：7

作者：

Rasniewski, Andrzej ^{[1
]}

机构：

[1] Warsaw Univ Technol, Inst Telecommun, PL-00665 Warsaw, Poland

来源：

MICROPROCESSORS AND MICROSYSTEMS | 2008年 / 32卷 / 5-6期

关键词：

FPGA; embedded memory; finite state machine (FSM); concurrent error detection (CED); single event upsets (SEUs);

D O I：

10.1016/j.micpro.2008.03.008

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We propose a cost-efficient concurrent error detection (CED) scheme for finite state machines (FSMs) designed for implementation with embedded memory blocks (EMBs) available in today's SRAM-based FPGAs. The proposed scheme is proven to detect each permanent or transient fault associated with a single input or output of any component of the circuit that results in its incorrect state or output. The experimental results obtained using our proprietary FSM synthesis tool show that despite the heterogeneous structure of the proposed CED scheme, the overhead is very low. For the examined benchmark circuits, the circuitry overhead in terms of extra EMBs is in the range of 6.3-56.3%, with an average value of 27.2%, whereas the combined overhead (EMBs and logic cells) calculated under pessimistic assumptions is in the range of 20.7-63.8%, with an average value of 32.2%. This compares favorably with the earlier proposed solutions applicable to conventional FSM designs based on gates and flip-flops for which an overhead exceeding 100% is quite typical. (C) 2008 Elsevier B.V. All rights reserved.

引用

页码：303 / 312

页数：10

共 41 条

[1] Entropy-driven parity-tree selection for low-overhead concurrent error detection in finite state machines [J].

Almukhaizim, Sobeeh ;

Drineas, Petros ;

Makris, Yiorgos .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, 25 (08) :1547-1554

[2]

*ALT, 2004, 357 ALT

[3]

[Anonymous], P IEEE INT TEST C

[4] Soft error mitigation for SRAM-based FPGAs [J].

Asadi, GH ;

Tahoori, MB .

23RD IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2005, :207-212

[5]

BELLATO M, 2004, IEEE DESIGN AUTOMATI, P188

[6] An integrated design approach for self-checking FPGAs [J].

Bolchini, C ;

Salice, F ;

Sciuto, D ;

Zavaglia, R .

18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2003, :443-450

[7] Designing self-checking FPGAs through error detection codes [J].

Bolchini, C ;

Salice, F ;

Sciuto, D .

17TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2002, :60-68

[8] Design of VHDL-based totally self-checking finite-state machine and data-path descriptions [J].

Bolchini, C ;

Montandon, R ;

Salice, F ;

Sciuto, D .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2000, 8 (01) :98-103

[9] TMR and partial dynamic reconfiguration to mitigate SEU faults in FPGAs [J].

Bolchini, Cristiana ;

Miele, Antonio ;

Santambrogio, Marco D. .

DFT 2007: 22ND IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2007, :87-95

[10]

Borowik G, 2007, IEEE INT SYMP DESIGN, P99

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