Interface State in Metal-Oxide-Nitride-Silicon Memories Induced by Hole Injection during Program/Erase Cycle Stress

被引：12

作者：

Fujii, Shosuke ^{[1
]}

Fujitsuka, Ryota ^{[2
]}

Sekine, Katsuyuki ^{[2
]}

Koyama, Masato ^{[1
]}

Yasuda, Naoki ^{[2
]}

机构：

[1] Toshiba Co Ltd, Adv LSI Technol Lab, Yokohama, Kanagawa 2358522, Japan

[2] Toshiba Co Ltd, Semicond & Storage Prod Co, Yokohama, Kanagawa 2358522, Japan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS | 2012年 / 51卷 / 12期

关键词：

GENERATION; CHARGE; TANOS; ERASE; NBTI;

D O I：

10.1143/JJAP.51.124302

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

The mechanism of interface-state generation in metal-oxide-nitride-silicon (MONOS) memories by program/erase (P/E) cycling was experimentally examined, using the charge measurement technique we developed that allows direct measurement of the amount of charges flowing during P/E operation. The amount of interface state was found to have a strong correlation with the amount of charges flowing during erase operation, irrespective of pulse voltage, pulse width and number of P/E cycles. It was also found that the amount of interface states generated by P/E cycling increases as hole fluence dominates erase operation. These findings suggest that hole injection from Si substrate, rather than electron detrapping from SiN layer or impact-ionized hot hole, is the main cause of the interface-state generation. (C) 2012 The Japan Society of Applied Physics

引用

页数：4

共 22 条

[11] COMPOSITION AND STRUCTURE CONTROL BY SOURCE GAS RATIO IN LPCVD SINX [J].

MAKINO, T .

JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1983, 130 (02) :450-455

[12]

Naruke K., 1988, International Electron Devices Meeting. Technical Digest (IEEE Cat. No.88CH2528-8), P424, DOI 10.1109/IEDM.1988.32846

[13]

Nicollian EH., 1982, MOS Physics and Technology

[14] A Comprehensive Understanding of the Erase of TANOS Memories Through Charge Separation Experiments and Simulations [J].

Padovani, Andrea ;

Arreghini, Antonio ;

Vandelli, Luca ;

Larcher, Luca ;

Van den Bosch, Geert ;

Pavan, Paolo ;

Van Houdt, Jan .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (09) :3147-3155

[15]

Sakamoto W., 2009, IEDM Tech. Dig, P831

[16] Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation [J].

Sandhya, C. ;

Oak, Apoorva B. ;

Chattar, Nihit ;

Ganguly, Udayan ;

Olsen, C. ;

Seutter, S. M. ;

Date, L. ;

Hung, R. ;

Vasi, Juzer ;

Mahapatra, Souvik .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (07) :1548-1558

[17] Experimental Assessment of Electrons and Holes in Erase Transient of TANOS and TANVaS Memories [J].

Suhane, Amit ;

Arreghini, Antonio ;

Van den Bosch, Geert ;

Vandelli, Luca ;

Padovani, Andrea ;

Breuil, Laurent ;

Larcher, Luca ;

De Meyer, Kristin ;

Van Houdt, Jan .

IEEE ELECTRON DEVICE LETTERS, 2010, 31 (09) :936-938

[18] Nitride engineering for improved erase performance and retention of TANOS NAND Flash memory [J].

Van den bosch, G. ;

Furnemont, A. ;

Zahid, M. B. ;

Degraeve, R. ;

Breuil, L. ;

Cacciato, A. ;

Rothschild, A. ;

Olsen, C. ;

Ganguly, U. ;

Van Houdt, J. .

2008 JOINT NON-VOLATILE SEMICONDUCTOR MEMORY WORKSHOP AND INTERNATIONAL CONFERENCE ON MEMORY TECHNOLOGY AND DESIGN, PROCEEDINGS, 2008, :128-+

[19]

van der Bent G., 2009, P IEEE MICR COMM ANT, P1

[20] Hole energy dependent interface trap generation in MOSFET Si/SiO2 interface [J].

Varghese, D ;

Mahapatra, S ;

Alam, MA .

IEEE ELECTRON DEVICE LETTERS, 2005, 26 (08) :572-574

← 1 2 3 →