Low-power multiplier with static decision for input manipulation

被引:0
作者
Riazati, M. [1 ]
Sobhani, A.
Mottaghi-Dastjerdi, M.
Afzali-Kusha, A.
Khakifirooz, A.
机构
[1] Univ Tehran, Nanoelectronics Ctr of Excellence, Sch Elect & Comp Engn, Tehran, Iran
[2] MIT, Dept Elect & Comp Sci, Cambridge, MA USA
来源
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年
关键词
D O I
10.1109/ISCAS.2006.1693186
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, a method to reduce the power consumption of low-power multipliers is proposed. A Decision Logic module decides about complementing the input before sending it to the multiplier core. The decision is based on minimizing the switching activity and hence the power consumption. The decision logic proposed in this work, unlike the conventional dynamic decision logic modules, uses a small look up table to make its decisions statically once for all the possible combinations on new input and old input. This feature has lead to the reduction of the power, delay, and complexity of the logic compared to its predecessors while the power saving is negligibly reduced.
引用
收藏
页码:2721 / 2724
页数:4
相关论文
共 9 条
  • [1] CHANDRAKASAN A, 1994, IEEE CUST INT CIRC C
  • [2] FUJINO M, IEEE CIRC SYST ISCAS, V5
  • [3] HOSSAIN R, 1994, 7 ANN IEEE INT, P19
  • [4] MOSHNYAGA VG, IEEE CIRC SYST ISCAS, V3
  • [5] OHBAN J, 2002, IEEE AS S PATH CIRC
  • [6] SEIDEL PM, 2002, 36 AS C, V1
  • [7] SONG M, 1995, IEEE INT SYMP CIRC S, P1568, DOI 10.1109/ISCAS.1995.523706
  • [8] TAEKYOON A, 1997, IEEE ELECT LETT, V33
  • [9] A low power-delay-product multiplier with dynamic operand exchange
    Tsai, CM
    Chiang, TM
    Hong, CH
    Kuo, KT
    Lin, RB
    [J]. 2000 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS: ELECTRONIC COMMUNICATION SYSTEMS, 2000, : 501 - 504