CHARACTERIZATION OF SILC AND ITS END-OF-LIFE RELIABILITY ASSESSMENT ON 45NM HIGH-K AND METAL-GATE TECHNOLOGY

被引：11

作者：

Pae, S. ^{[1
,2
]}

Ghani, T. ^{[2
]}

Hattendorf, M.

Hicks, J. ^{[1
]}

Jopling, J. ^{[1
]}

Maiz, J. ^{[1
]}

Mistry, K. ^{[2
]}

O'Donnell, J. ^{[1
]}

Prasad, C. ^{[1
]}

Wiedemer, J. ^{[2
]}

Xu, J. ^{[1
]}

机构：

[1] Intel Corp, Log Technol Dev Q&R, 5200 NE Elam Young Pkwy,RA3-402, Hillsboro, OR 97124 USA

[2] Portland Technol Dev, Hillsboro, OR 97124 USA

来源：

2009 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, VOLS 1 AND 2 | 2009年

关键词：

High-K dielectric; Metal gate; Transistor; Reliability; TDDB; SILC; NMOS PBTI; BREAKDOWN; STACKS;

D O I：

10.1109/IRPS.2009.5173303

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Stress Induced Leakage Current (SILC) has been observed on non-optimized high-K (HK) and metal-gate (MG) transistors. Large NMOS PBTI degradation and correlation to SILC increase on such gate stack is a result of large trap generations in the bulk-HK. This poses a long term reliability concern on product standby power and can limit the operating voltage if not suppressed. On an optimized HK+MG process, we demonstrate that SILC has been suppressed. The transistor level SILC data, model and Product burn-in stress data support this. With optimized process, SILC has no impact on products made of 45nm HK+MG transistors.

引用

页码：499 / +

页数：2

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