A floating gate design for electrostatic discharge protection circuits

被引：3

作者：

Chou, Hung-Mu

Lee, Jam-Wen

Li, Yiming

机构：

[1] Natl Chiao Tung Univ, Microelect & Informat Syst Res Ctr, Hsinchu 300, Taiwan

[2] Natl Chiao Tung Univ, Dept Commun Engn, Hsinchu 300, Taiwan

来源：

INTEGRATION-THE VLSI JOURNAL | 2007年 / 40卷 / 02期

关键词：

electrostatic discharge; robustness; floating gate; gate grounded; leakage current; negatively biased circuit; sub-100 nm CMOS device and circuit;

D O I：

10.1016/j.vlsi.2006.02.005

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a circuit design method for electrostatic discharge (ESD) protection is presented. It considers the gate floating state for ESD protection and negatively gate biased for leakage suppression under normal operations. The circuit is achieved by adding a switch device and a negatively biased circuit at the gate of ESD protection devices. Robustness and leakage of ESD protection circuit are improved. The circuit suits thin thickness of gate oxide of complementary metal oxide semiconductor (CMOS) devices due to an elimination of oxide damage. This approach benefits design of very large-scaled integration circuit and implementation of system-on-chip with sub-100 nm CMOS devices. (c) 2006 Elsevier B.V. All rights reserved.

引用

页码：161 / 166

页数：6