Optimum Design of Conversion Gain and Full Well Capacity in CMOS Image Sensor With Lateral Overflow Integration Capacitor

被引：20

作者：

Akahane, Nana ^{[1
]}

Adachi, Satoru ^{[2
]}

Mizobuchi, Koichi ^{[2
]}

Sugawa, Shigetoshi ^{[1
]}

机构：

[1] Tohoku Univ, Grad Sch Engn, Sendai, Miyagi 9808579, Japan

[2] Texas Instruments Japan Ltd, Ibaraki 3000496, Japan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2009年 / 56卷 / 11期

基金：

日本学术振兴会;

关键词：

CMOS image sensor; conversion gain (CG); full well capacity (FWC); signal-to-noise ratio (SNR);

D O I：

10.1109/TED.2009.2030550

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An optimum design theory to clarify a possible limit of achieving both high conversion gain (CG) and full well capacity (FWC) at the same time in a CMOS image sensor with a lateral overflow integration capacitor (LOFIC) in a pixel is discussed. The possible limit of both high CG and high FWC is theoretically derived from a signal-to-noise-ratio (SNR) formula at a switching point from a low light signal (S1) to a bright one (S2). Based on this theory, a 1/4-in VGA-format 5.6-mu m-pixel-pitch CMOS image sensor has been fabricated through a 0.18-mu m 2P3M CMOS technology. A high-quality wide-dynamic-range image sensing has been demonstrated with no significant visible noise, achieving over 32 dB of SNR for an 18% gray card.

引用

页码：2429 / 2435

页数：7