Determination of safe reliability region over temperature and current density for through wafer vias

被引：0
|
作者：
Whitman, Charles S. [1 ]
Meeder, Michael G. [1 ]
Zampardi, Peter J. [1 ]
机构：
[1] Qorvo, 7628 Thorndike Rd, Greensboro, NC 27409 USA
来源：
MICROELECTRONICS RELIABILITY | 2017年 / 68卷
关键词：
Through-wafer via; Backside via; Black's equation; Likelihood ratio; FIT rate;
D O I：
10.1016/j.microrel.2016.09.011
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Circular and slot backside vias are stressed over current and temperature and the resulting failure times are fitted to Black's equation. Contour plots of the FIT rate are generated and the reliability of circular and slot vias are compared. It is demonstrated that in most cases the FIT rate of the circular via is statistically significantly lower than that of the slot via. However, both types are easily able to meet a goal of 100 FITs in 10 years at T = 125 degrees C and J = 0.25 x 10(6) A/cm(2). The contour map of the FIT rate defines the region where the via can operate reliably. By use of the 95% upper confidence bound, the region of safe operation is reduced in size, adding a layer of margin to the prediction of via reliability. The approach described here provides a "reliability map" for designers allowing trade-offs between temperature current to be made when designing for high reliability. (C) 2016 Published by Elsevier Ltd.
引用
收藏
页码：5 / 12
页数：8
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