Determination of safe reliability region over temperature and current density for through wafer vias

被引：0

作者：

Whitman, Charles S. ^{[1
]}

Meeder, Michael G. ^{[1
]}

Zampardi, Peter J. ^{[1
]}

机构：

[1] Qorvo, 7628 Thorndike Rd, Greensboro, NC 27409 USA

来源：

MICROELECTRONICS RELIABILITY | 2017年 / 68卷

关键词：

Through-wafer via; Backside via; Black's equation; Likelihood ratio; FIT rate;

D O I：

10.1016/j.microrel.2016.09.011

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Circular and slot backside vias are stressed over current and temperature and the resulting failure times are fitted to Black's equation. Contour plots of the FIT rate are generated and the reliability of circular and slot vias are compared. It is demonstrated that in most cases the FIT rate of the circular via is statistically significantly lower than that of the slot via. However, both types are easily able to meet a goal of 100 FITs in 10 years at T = 125 degrees C and J = 0.25 x 10(6) A/cm(2). The contour map of the FIT rate defines the region where the via can operate reliably. By use of the 95% upper confidence bound, the region of safe operation is reduced in size, adding a layer of margin to the prediction of via reliability. The approach described here provides a "reliability map" for designers allowing trade-offs between temperature current to be made when designing for high reliability. (C) 2016 Published by Elsevier Ltd.

引用

页码：5 / 12

页数：8

共 50 条

[1] Reliability study of Through Glass Vias under high current density
Xiang, Junshan
Chen, Hongtao
Wang, Haozhong
Yang, Xiaofeng
2023 24TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT, 2023,
[2] Mechanical reliability of silicon wafers with through-wafer vias for wafer-level packaging
Polyakov, A
Bartek, M
Burghartz, JN
MICROELECTRONICS RELIABILITY, 2002, 42 (9-11) : 1783 - 1788
[3] DETERMINATION OF THE TEMPERATURE RISE AND THE MAXIMUM SAFE CURRENT THROUGH MULTICONDUCTOR ELECTRIC CABLES
ISKENDERIAN, HP
HORVATH, WJ
JOURNAL OF APPLIED PHYSICS, 1946, 17 (04) : 255 - 262
[4] High density, high aspect ratio through-wafer electrical interconnect vias for MEMS packaging
Ok, SJ
Kim, CH
Baldwin, DF
IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2003, 26 (03): : 302 - 309
[5] Reliability of Copper Wirebonds over Through-Silicon Vias for SiGe Power Amplifiers
Gambino, Jeff
Graf, Rich
Guthrie, Bill
Salimeno, Jim
Nuzback, Jerry
2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2015, : 656 - 660
[6] Diffusion resistance of low temperature chemical vapor deposition dielectrics for multiple through silicon vias on bumpless wafer-on-wafer technology
Fujitsu Laboratories Ltd., Atsugi, Kanagawa 243-0197, Japan
不详
不详
Jpn. J. Appl. Phys., 5 PART 2
[7] Diffusion Resistance of Low Temperature Chemical Vapor Deposition Dielectrics for Multiple Through Silicon Vias on Bumpless Wafer-on-Wafer Technology
Kitada, Hideki
Maeda, Nobuhide
Fujimoto, Koji
Mizushima, Yoriko
Nakata, Yoshihiro
Nakamura, Tomoji
Ohba, Takayuki
JAPANESE JOURNAL OF APPLIED PHYSICS, 2011, 50 (05)
[8] Coupled simulation to determine the impact of across wafer variations in oxide PECVD on electrical and reliability parameters of through-silicon vias
Baer, E.
Evanschitzky, P.
Lorenz, J.
Roger, F.
Minixhofer, R.
Filipovic, L.
de Orio, R. L.
Selberherr, S.
MICROELECTRONIC ENGINEERING, 2015, 137 : 141 - 145
[9] Reliability testing of through-silicon vias for high-current 3D applications
Wright, Steven L.
Andry, Paul S.
Sprogis, Edmund
Dang, Bing
Polastre, Robert J.
58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS, 2008, : 879 - +
[10] Reliability Challenges in Advanced 3D Technologies: The Case of Through Silicon Vias and SiCN-SiCN Wafer-to-Wafer Hybrid-Bonding Technologies
Chery, Emmanuel
Fohn, Corinna
De Messemaeker, Joke
Beyne, Eric
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2023, 23 (04) : 615 - 622

← 1 2 3 4 5 →