DETECTING HARDWARE COVERT TIMING CHANNELS

被引：19
作者：
Venkataramani, Guru [1 ]
Chen, Jie [2 ]
Doroslovacki, Milos [1 ]
机构：
[1] George Washington Univ, Dept Elect & Comp Engn, Washington, DC 20052 USA
[2] George Washington Univ, Washington, DC 20052 USA
来源：
IEEE MICRO | 2016年 / 36卷 / 05期
基金：
美国国家科学基金会;
关键词：
algorithms; covert channels; detection; hardware timing channels; security;
D O I：
10.1109/MM.2016.83
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Many popular computing environments are vulnerable to covert timing channels. With improvements in software confinement mechanisms, shared processor hardware structures will be natural targets for such an attack. The authors present a microarchitecture-level framework that detects the possible presence of covert timing channels on shared hardware. Experimental results demonstrate their ability to detect different types of covert timing channels on various hardware structures and communication patterns.
引用
收藏
页码：17 / 27
页数：11
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