A complex polynomial predistorter chip in CMOS for baseband or IF linearization of RF power amplifiers

This paper describes the implementation of a 5:th order complex polynomial predistorter chip in CMOS for linearization of RF power amplifiers. The architecture chosen allows operation either at baseband or IE The chip was implemented in a 0.8 mu m CMOS process and operates at 3.3V supply voltage with 60 mW power consumption. The special architecture of the polynomial predistorter is exploited to reduce the complexity and current consumption of individual blocks. Two-tone measurements performed at an IF of 200 MHz demonstrates that third order intermodulation products can be suppressed by more than 30 dB.