On the Electrical Characterization of Grain Boundaries in Multicrystalline Silicon

被引：3

作者：

Chen, J. ^{[1
]}

Cornagliotti, E. ^{[2
]}

Hieckmann, E. ^{[1
]}

Behrendt, S. ^{[1
]}

Weber, J. ^{[1
]}

Simoen, E. ^{[2
]}

Poortmans, J. ^{[2
]}

机构：

[1] Tech Univ Dresden, D-01062 Dresden, Germany

[2] IMEC, B-3001 Louvain, Belgium

来源：

PHOTOVOLTAICS FOR THE 21ST CENTURY 6 | 2011年 / 33卷 / 17期

关键词：

METAL IMPURITIES; DISLOCATIONS; DEFECTS; DLTS;

D O I：

10.1149/1.3553349

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

Impurity decoration of grain boundaries (GB) introduces deep levels and enhances their recombination activity. In this study we use the standard DLTS technique to investigate the influence of the GB structure on the electrical properties of mc-Si. The detected DLTS spectra have an opposite signal compared to the usually known majority carrier peaks of deep levels, but standard DLTS analysis can yield trap energies and capture cross sections. By comparing the properties between GB and intra-grain regions with similar minority carrier lifetime, it is considered that the DLTS signals might be due to traps generated in the extended defects present both at GBs and grains. It is observed that Sigma(3) GB has deep level traps at the same energy level as Sigma(9) GB, while the trap concentration in the former one is lower than the latter. Furthermore, a phosphorous gettering treatment can reduce the recombination activities both in the grains and at the GBs.

引用

页码：71 / 80

页数：10

共 18 条

[1]

[Anonymous], 2013, Physical Foundations of Materials Science, DOI DOI 10.1007/978-3-662-09291-0

[2] Electron-beam-induced current study of grain boundaries in multicrystalline silicon [J].