Automatic Integration of Hardware Descriptions into System-Level Models

被引：0

作者：

Goergen, Ralph ^{[1
]}

Oetjens, Jan-Hendrik ^{[2
]}

Nebel, Wolfgang ^{[3
]}

机构：

[1] OFFIS Inst Informat Technol, D-26121 Oldenburg, Germany

[2] Robert Bosch GmbH, D-72762 Reutlingen, Germany

[3] Carl von Ossietzky Univ Oldenburg, D-26111 Oldenburg, Germany

来源：

2012 IEEE 15TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS) | 2012年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present a flow for integrating hardware descriptions into Simulink simulations. It enables the automatic generation of a Simulink component out of a hardware component model given as RT level VHDL. The approach is based on two steps. The first step transforms the VHDL model to SystemC. In contrast to existing VHDL-to-SystemC transformation tools, the readability and configurability of the input model is preserved. In addition, our approach yields a more exact model, as a custom designed VHDL-like data-type system is employed. The second step generates a specific wrapper to allow the use of the component in a Simulink simulation. This transformation strategy will be evaluated with two industrial automotive electronics hardware designs.

引用

页码：105 / 110

页数：6