Rapid circuit-based optimization of low operational power CMOS devices

被引：0

作者：

Christie, P. ^{[1
]}

Nackaerts, A. ^{[3
]}

Hoffmann, T. ^{[3
]}

Kumar, A. ^{[2
]}

机构：

[1] NXP TSMC Res Ctr, Leuven, Belgium

[2] NXP Semicond, Eindhoven, Netherlands

[3] IMEC, Leuven, Belgium

来源：

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 | 2007年

关键词：

D O I：

10.1109/IEDM.2007.4419003

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

We demonstrate: (i) a silicon-calibrated, low computational complexity Verilog-A MOS model coupled to rapid library generation and characterization tool set within a commercial-grade design flow, (ii) the use of this design flow for the evaluation of TCAD-based transistors in high complexity circuits with iteration times of less than three hours, (iii) the design of 16-bit multiplier circuits with low operational (static + dynamic) power CMOS devices with power savings of 84% and 76% at 25 degrees C and 60 degrees C, respectively, compared to an unmodified 70nm gate length CMOS process.

引用

页码：573 / +

页数：2

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