Trap energetic and spatial localization in buried-gate 6H-SiC JFETs by means of numerical device simulation

被引：1

作者：

Verzellesi, G ^{[1
]}

Meneghesso, G

Cavallini, A

Zanoni, E

机构：

[1] Univ Modena & Reggio Emilia, Dept Sci & Ingn, Modena, Italy

[2] INFM, I-41100 Modena, Italy

[3] Univ Padua, I-35131 Padua, Italy

[4] INFM, Padua, Italy

[5] Univ Bologna, Dipartimento Fis, I-40126 Bologna, Italy

[6] INFM, Bologna, Italy

来源：

IEEE ELECTRON DEVICE LETTERS | 2001年 / 22卷 / 12期

关键词：

DLTS; JFET; SiC; 2-D simulations;

D O I：

10.1109/55.974583

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Deep levels with activation energies up to 0.59 eV have been revealed in buried gate, n-channel 6H-silicon carbide JFETs, by means of capacitance- and current-mode deep level transient spectroscopy. Numerical device simulations of the drain-current transients following a gate-to-source voltage step have enabled us to localize the different deep levels both energetically and spatially.

引用

页码：579 / 581

页数：3

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