Parallel architecture and optimization for discrete-event simulation of spike neural networks

被引:14
作者
Tang YuHua [1 ,2 ]
Zhang BaiDa [1 ,2 ]
Wu JunJie [1 ,2 ]
Hu TianJiang [3 ]
Zhou Jing [1 ,2 ]
Liu FuDong [1 ,2 ]
机构
[1] Natl Univ Def Technol, Sch Comp, Dept Comp Sci & Technol, Changsha 410073, Hunan, Peoples R China
[2] Natl Univ Def Technol, State Key Lab High Performance Comp, Changsha 410073, Hunan, Peoples R China
[3] Natl Univ Def Technol, Coll Mechatron Engn & Automat, Changsha 410073, Hunan, Peoples R China
基金
中国国家自然科学基金;
关键词
spike neural network; discrete event simulation; intelligent parallelization framework; NEURONS; MULTIPROCESSOR; INTEGRATE; COMPUTERS;
D O I
10.1007/s11431-012-5084-2
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Spike neural networks are inspired by animal brains, and outperform traditional neural networks on complicated tasks. However, spike neural networks are usually used on a large scale, and they cannot be computed on commercial, off-the-shelf computers. A parallel architecture is proposed and developed for discrete-event simulations of spike neural networks. Furthermore, mechanisms for both parallelism degree estimation and dynamic load balance are emphasized with theoretical and computational analysis. Simulation results show the effectiveness of the proposed parallelized spike neural network system and its corresponding support components.
引用
收藏
页码:509 / 517
页数:9
相关论文
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