On Enduring More Data Through Enabling Page Rewrite Capability on Multi-level-cell Flash Memory

被引:1
作者
Chang, Yu-Ming [1 ]
Ho, Chien-Chung [2 ]
Tsao, Che-Wei [3 ]
Liao, Shu-Hsien [4 ]
Wang, Wei-Chen [4 ,5 ]
Kuo, Tei-Wei [4 ,6 ]
Chang, Yuan-Hao [3 ]
机构
[1] Wolley Inc, Hsinchu, Taiwan
[2] Natl Cheng Kung Univ, Tainan, Taiwan
[3] Acad Sinica, Taipei, Taiwan
[4] Natl Taiwan Univ, Taipei, Taiwan
[5] Macronix Int Co Ltd, Taipei, Taiwan
[6] City Univ Hong Kong, Taipei, Taiwan
来源
37TH ANNUAL ACM SYMPOSIUM ON APPLIED COMPUTING | 2022年
关键词
Page Rewrite; Multi-level-cell; Endurance; Disturbance;
D O I
10.1145/3477314.3507088
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
The technology of NAND flash memory grows swiftly in response to the huge and rapidly changing storage market in recent years. Meanwhile, the demand for large amounts of data is also growing at an unprecedented scale. How to store more and more data over flash-based systems in a cost-effective way presents immense pressure and challenges to the system design. This motivates us to propose a breakthrough solution on the existing multi-level-cell flash memories such as TLC, being adopted in the mainstream solidstate drives. More specifically, we propose a durable management design through enabling page rewrite capability and incorporate it with the existing flash translation layer to achieve enduring more data written, even beyond the theoretical limit. Moreover, our management design further considers the adverse effect brought by disturbance, which could usually deteriorate the data correctness. The encouraging results through a series of experiments demonstrate the feasibility and the capability of our design. With the best setting we studied, the total amount of data that can be written into the system could be improved up to 2.14 times the baseline without adding any hardware cost.
引用
收藏
页码:107 / 115
页数:9
相关论文
共 21 条
[1]  
[Anonymous], 2011, JESD218 JEDEC
[2]  
Ban Amir, 1995, US Patent, Patent No. [5,404,485, 5404485]
[3]  
Cai Y, 2013, 2013 IEEE 31ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), P123, DOI 10.1109/ICCD.2013.6657034
[4]  
Chang Y., 2016, HARDWARE SOFTWARE CO, P1
[5]   Performance Enhancement of 3-D NAND Flash Featuring a Two-Step Dummy Wordline Program Waveform and Pair-Bitline Program Scheme [J].
Chen, Wei-Chen ;
Lue, Hang-Ting ;
Hsieh, Chih-Chang ;
Wang, Keh-Chung ;
Lu, Chih-Yuan .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (01) :99-104
[6]  
Chen Y, 2016, PROC IEEE ACM CODES
[7]   Constructing Large, Durable and Fast SSD System via Reprogramming 3D TLC Flash Memory [J].
Gao, Congming ;
Ye, Min ;
Li, Qiao ;
Xue, Chun Jason ;
Zhang, Youtao ;
Shi, Liang ;
Yang, Jun .
MICRO'52: THE 52ND ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, 2019, :493-505
[8]   A Block-Level Log-Block Management Scheme for MLC NAND Flash Memory Storage Systems [J].
Guan, Yong ;
Wang, Guohui ;
Ma, Chenlin ;
Chen, Renhai ;
Wang, Yi ;
Shao, Zili .
IEEE TRANSACTIONS ON COMPUTERS, 2017, 66 (09) :1464-1477
[9]   DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings [J].
Gupta, Aayush ;
Kim, Youngjae ;
Urgaonkar, Bhuvan .
ACM SIGPLAN NOTICES, 2009, 44 (03) :229-240
[10]   A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory [J].
Kim, Chulbum ;
Kim, Doo-Hyun ;
Jeong, Woopyo ;
Kim, Hyun-Jin ;
Park, Il Han ;
Park, Hyun-Wook ;
Lee, JongHoon ;
Park, JiYoon ;
Ahn, Yang-Lo ;
Lee, Ji Young ;
Kim, Seung-Bum ;
Yoon, Hyunjun ;
Yu, Jae Doeg ;
Choi, Nayoung ;
Kim, NaHyun ;
Jang, Hwajun ;
Park, JongHoon ;
Song, Seunghwan ;
Park, YongHa ;
Bang, Jinbae ;
Hong, Sanggi ;
Choi, Youngdon ;
Kim, Moo-Sung ;
Kim, Hyunggon ;
Kwak, Pansuk ;
Ihm, Jeong-Don ;
Byeon, Dae Seok ;
Lee, Jin-Yub ;
Park, Ki-Tae ;
Kyung, Kye-Hyun .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53 (01) :124-133