Advanced failure detection techniques in deep submicron CMOS integrated circuits

被引:0
|
作者
Rubio, A [1 ]
Altet, J [1 ]
Mateo, D [1 ]
机构
[1] Univ Politecn Cataluna, Dept Elect Engn, Grp Design & Test High Performance Circuits, ES-08034 Barcelona, Spain
关键词
D O I
10.1016/S0026-2714(99)00122-5
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The test of present integrated circuits exhibits many confining aspects, among them the adequate selection of the observable variables, the use of combined testing approaches, an each time more restricted controllability and observability (physically and electrically) and finally the required testing time. In the paper these points are discussed and different nowadays-promising techniques exposed. Complementarily to the logic output variable analysis (both value and delay) three efficient detection and localisation techniques can be considered that are contemplated in this work: the detection of light, heat and leakage currents due to the presence of failures. In most of the cases it is not possible to differentiate clearly, like was in the past, the production testing, the in-field testing, the test and the localisation of the failure, making each time closer the fields of testing and failure analysis. (C) 1999 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码:909 / 918
页数:10
相关论文
共 50 条
  • [21] RADIATION FAILURE MODES IN CMOS INTEGRATED-CIRCUITS
    BURGHARD, RA
    GWYN, CW
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1973, NS20 (06) : 300 - 306
  • [22] Crosstalk Noise and Signal Propagation Delay Analysis in Submicron CMOS Integrated Circuits
    Bouazza, Ahlam Guen
    Bouazza, Benyounes
    2012 6TH INTERNATIONAL CONFERENCE ON SCIENCES OF ELECTRONICS, TECHNOLOGIES OF INFORMATION AND TELECOMMUNICATIONS (SETIT), 2012, : 155 - 160
  • [23] AN INVESTIGATION OF HOT-CARRIER EFFECTS IN SUBMICRON CMOS INTEGRATED-CIRCUITS
    FANG, P
    RAKKHIT, R
    YUE, JT
    MICROELECTRONICS AND RELIABILITY, 1993, 33 (11-12): : 1713 - 1727
  • [24] Static power optimization of deep submicron CMOS circuits for dual VT technology
    Wang, Q
    Vrudhula, SBK
    1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS, 1998, : 490 - 496
  • [25] Challenges to accuracy for the design of deep-submicron RF-CMOS circuits
    Yoshitomi, Sadayuki
    PROCEEDINGS OF THE ASP-DAC 2007, 2007, : 438 - 441
  • [26] Impact Analysis of Resistive Bridge within Deep Submicron Secured CMOS Circuits
    Abdelmalek, G. Ait
    Ziani, R.
    2014 9TH INTERNATIONAL DESIGN & TEST SYMPOSIUM (IDT), 2014, : 112 - 117
  • [27] CAD Tools for Analysis of Process Variability Effects in Deep Submicron CMOS Circuits
    Kuzmicz, W.
    Piwowarska, E.
    Pfitzner, A.
    Kasprowicz, D.
    2008 IEEE REGION 8 INTERNATIONAL CONFERENCE ON COMPUTATIONAL TECHNOLOGIES IN ELECTRICAL AND ELECTRONICS ENGINEERING: SIBIRCON 2008, PROCEEDINGS, 2008, : 304 - 309
  • [28] A comprehensive review of endpoint detection in chemical mechanical planarization for deep-submicron integrated circuits manufacturing
    Hocheng, H
    Huang, YL
    INTERNATIONAL JOURNAL OF MATERIALS & PRODUCT TECHNOLOGY, 2003, 18 (4-6): : 469 - 486
  • [29] Photodiodes in Deep Submicron CMOS Process for Fully Integrated Optical Receivers
    Ahmad, Waqas
    Tormanen, Markus
    Sjoland, Henrik
    2013 PROCEEDINGS OF THE EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2013, : 135 - 138
  • [30] On the Signal Propagation Delay Study for the Deep Submicron CMOS Integrated Circuit
    Sahraoui, H.
    Bouazza, A. Guen
    Bouazza, B.
    Ghaffour, K. E.
    Sari, N. E. Chabane
    AFRICAN REVIEW OF PHYSICS, 2008, 2 : 87 - 88