Exploring Hierarchical, Cluster based 3D Topologies for 3D NoC

被引：3

作者：

Viswanathan, N. ^{[1
]}

Paramasivam, K. ^{[2
]}

Somasundaram, K. ^{[3
]}

机构：

[1] Mahendra Engn Coll, ECE, Namakkal 637503, India

[2] Bannari Amman Inst Technol, ECE, Erode 638401, India

[3] Amrita Vishwa Vidyapeetham, Dept Math, Coimbatore 641112, Tamil Nadu, India

来源：

INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY AND SYSTEM DESIGN 2011 | 2012年 / 30卷

关键词：

3D NoC; latency; traffic rate; buffer size; TSVs; IP blocks; network diameter; energy dissipation;

D O I：

10.1016/j.proeng.2012.01.905

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Network-on-Chip (NoC) has been recognized as an effective solution for complex on-chip communication problems faced in System-on-Chips (SoCs). Network topology, switching mechanism and routing algorithms are the key research area in NoC. In recent years, since the inception of Through-Silicon-Vias (TSVs) to realize vertical channel, 3D stacked NoC architecture attracts a lot of interest as it offers improved performance and shorter global interconnect. In this paper, two clustered 3D network topologies (3D-ST and 3D-RNT) and hierarchical, cluster based routing algorithms are presented. Experimental results on various parameters like latency, drop probability and energy dissipation are compared for the two topologies. It is demonstrated from the analysis that 3D-RNT is an appropriate candidate for 3D NoC provided interlayer communications are not very frequent. (C) 2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of ICCTSD 2011

引用

页码：606 / 615

页数：10

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