(ZrO2)x(La2O3)1-x Alloy as High-k Gate Dielectric for Advanced CMOS Devices

An amorphous (ZrO2)(x)(La2O3)(1-x) alloy formed by deposition of ZrO2/La2O3/ZrO2 laminate and a subsequent annealing was employed as the gate dielectric for MOS devices and the impact of a SiON interfacial layer on device performance was also explored in this work. The (ZrO2)(x)(La2O3)(1-x) alloy is found to have a high k value of 26.9 and tiny amount of bulk traps, both of which are very desirable for advanced high-k gate dielectrics. In addition, it is observed that the thermally grown SiON interfacial layer can prevent the formation of a silicide (ZrSi) and/or lower-k silicate (ZrSiO4) film during the subsequent annealing, which would cause poor interfacial qualities. By integrating the (ZrO2)(x)(La2O3)(1-x) alloy and SiON interfacial layer, MOS devices demonstrate a leakage current of 3x10(-9) A/cm(2) at gate voltage (V-g) of -1 V with EOT of 2.31 nm and this performance is superior to other high-k gate dielectrics. Most importantly, the process of forming the (ZrO2)(x)(La2O3)(1-x)/SiON stack is compatible with existent ultra large scale integration (ULSI) technology and has high potential to be adopted for further advanced complementary metal-oxide-semiconductor (CMOS) devices.