A High parallelism hardware architecture design of the H.264/AVC integer motion estimation for applications in real-time DTTV transmissions

The H.264/AVC is the Standard Video Format used by the SBTVD (Sistema Brasileiro de Televisdo Digital), with presence in almost all the countries in South America, that allows transmissions in Full High Definition (Full HD) video quality. So this work presents a hardware architecture design of the Motion Estimation algorithm used in the Standard, as the higher computational processing is located in this part, so we take advantage of the high parallelism characteristics of the designs made in hardware to achieve faster processing and hence real-time broadcasts. The design was described using VHDL and synthesized to the Altera Cyclone II FPGA being able to process Full HD video (1920x1080 pixels) in real-time. The results establish a maximum operation frequency of 183.55 MHz, and at this speed it can process 35 frames per second. (C) 2014 Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license (hllp://crealivecommons.org/licenses/by-nc-nd/3.0/). Peer-review under responsibility of ISLE Institut Superior de Engenharia de Lisboa, Lisbon, PORTUGAL.