Design of an efficient digital down-converter for a SDR-based DVB-S receiver

被引:0
作者
Perez-Pascual, A. [1 ]
Sansaloni, T. [1 ]
Torres, V. [1 ]
Almenar, V. [1 ]
Valls, J. [1 ]
机构
[1] Univ Politecn Valencia, Inst Telecommun & Multimedia Applicat, Gandia 46730, Spain
来源
2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3 | 2007年
关键词
D O I
10.1109/ECCTD.2007.4529585
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents the design of an area-power efficient digital down-converter suitable for broadband communication systems. The DVB-S standard has been used as a design example. It has been shown that by selecting a band-pass sampling to generate only one spectral image, the case in which the relationship between the digital carrier frequency and the sampling frequency is 1/4, not only gives the smallest area but the lowest power consumption.
引用
收藏
页码:256 / 259
页数:4
相关论文
共 33 条
[21]   Wideband 70dB CMOS digital variable gain amplifier design for DVB-T receiver's AGC [J].
Wang, CC ;
Lee, CL ;
Lin, LP ;
Tseng, YL .
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, :356-359
[22]   A low power digitally-enhanced SASP-based receiver architecture for mobile DVB-S applications in the Ku-band (10.7-12.75 GHz) [J].
Fouque, Andree ;
Rivet, Francois ;
Fadhuile, Francois ;
Deval, Yann ;
Begueret, Jean-Baptiste ;
Belot, Didier .
2011 IEEE RADIO AND WIRELESS SYMPOSIUM (RWS), 2011, :275-278
[23]   Design and test methodology for an analog-to-digital converter multichip module for experimental all-digital radar receiver operating at 2 gigasamples/s [J].
Thompson, RL ;
Amundsen, ELH ;
Schaefer, TM ;
Riemer, PJ ;
Degerstrom, MJ ;
Gilbert, BK .
IEEE TRANSACTIONS ON ADVANCED PACKAGING, 1999, 22 (04) :649-664
[24]   A low-power 2.4-GHz receiver front-end with a complementary series feedback LNA and a current-reused passive down-converter based on gm-boosted TIA for WSN applications [J].
Zhu, Dezheng ;
Wang, Yuxuan ;
Peng, Chenglei ;
Pan, Hongbing ;
Cai, Zhikuang .
IEICE ELECTRONICS EXPRESS, 2020, 17 (23)
[25]   A low-power 2.4-GHz receiver front-end with a complementary series feedback LNA and a current-reused passive down-converter based on gm-boosted TIA for WSN applications [J].
Zhu D. ;
Wang Y. ;
Peng C. ;
Pan H. ;
Cai Z. .
IEICE Electronics Express, 2021, 17 (23)
[26]   A Cost-Efficient Fully Synthesizable Stochastic Time-to-Digital Converter Design Based on Integral Nonlinearity Scrambling [J].
Zhang, Qiaochu ;
Su, Shiyu ;
Chen, Mike Shuo-Wei .
PROCEEDINGS OF THE 59TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC 2022, 2022, :1021-1026
[27]   Design Successive Approximation Register Analog-To-Digital Converter with Vcm-Based Method for M-PAM Receiver and Sensor Application [J].
Lai, Wen-Cheng ;
Lee, Ho Chang .
2016 10TH INTERNATIONAL CONFERENCE ON SENSING TECHNOLOGY (ICST), 2016,
[28]   A top-down design verification based on reuse modular and parametric behavioral modeling for subranging pipelined analog-to-digital converter [J].
Wang, J. ;
Siek, L. ;
Filippi, R. ;
Ng, K. A. .
2007 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, VOLS 1 AND 2, 2007, :378-+
[29]   Design Successive Approximation Register Analog-To-Digital Converter with Vcm-Based Method for M-PAM Receiver and Computational Intelligence Application [J].
Lai, Wen Cheng .
2015 10TH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS AND KNOWLEDGE ENGINEERING (ISKE), 2015, :567-570
[30]   Design of an efficient optical analog-to-digital converter using silicon waveguide based all-optical synchronous up counter [J].
Rao, Vartika ;
Mandal, Sanjoy .
OPTICAL AND QUANTUM ELECTRONICS, 2022, 54 (11)