Unified Inductance Calculations for On-Chip Planar Spirals

被引:1
|
作者
Xie, Shuangwen [1 ,2 ]
Fu, Jun [1 ,2 ]
机构
[1] Tsinghua Univ, Sch Integrated Circuits, Beijing, Peoples R China
[2] Tsinghua Univ, BNRist, Beijing, Peoples R China
关键词
on-chip planar inductors; inductance calculations; unified form; integrated circuit design;
D O I
10.1109/ICECS202256217.2022.9971015
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Four unified calculations with only coefficients dependent are proposed for the DC inductance of common on-chip spirals of square, hexagon, octagon and circle. The first two algorithms are based on the derivation of Neumann integral, which evaluate the inductance according to turns rather than discrete segments. The latter two expressions are obtained from a simple modification of published expressions by considering the metal thickness. An automatic script is employed to generate hundreds of thousands of inductor layouts for electromagnetic (EM) simulation. By comparison with the simulated predictions, the proposed calculations show typical errors within around 1-3%, which are competitive for the modeling, design and optimization of integrated inductors.
引用
收藏
页数:4
相关论文
共 50 条
  • [1] On the extraction of on-chip inductance
    Ismail, YI
    Friedman, EG
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2003, 12 (01) : 31 - 40
  • [2] Inductance Modeling for On-Chip Interconnects
    Shang-Wei Tu
    Wen-Zen Shen
    Yao-Wen Chang
    Tai-Chen Chen
    Jing-Yang Jou
    Analog Integrated Circuits and Signal Processing, 2003, 35 : 65 - 78
  • [3] Grasping the impact of on-chip inductance
    Massoud, Yehia
    Ismail, Yehea
    IEEE Circuits and Devices Magazine, 2001, 17 (04): : 14 - 21
  • [4] On-chip inductance modeling and analysis
    Gala, K
    Zolotov, V
    Panda, R
    Young, B
    Wang, JF
    Blaauw, D
    37TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2000, 2000, : 63 - 68
  • [5] Inductance analysis of on-chip interconnects
    Kundu, S
    Ghoshal, U
    EUROPEAN DESIGN & TEST CONFERENCE - ED&TC 97, PROCEEDINGS, 1997, : 252 - 255
  • [6] Inductance modeling for on-chip interconnects
    Tu, SW
    Shen, WZ
    Chang, YW
    Chen, TC
    Jou, JY
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2003, 35 (01) : 65 - 78
  • [7] On-chip inductance cons and pros
    Ismail, YI
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10 (06) : 685 - 694
  • [8] Inductance modeling for on-chip interconnects
    Tu, SW
    Shen, WZ
    Chang, YW
    Chen, TC
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, PROCEEDINGS, 2002, : 787 - 790
  • [9] Simple and Accurate Radio Frequency Inductance Expression for On-chip Planar Spiral Inductors
    Xiao, Qirong
    Luo, Tianxing
    Shi, Yanling
    Chen, Dawei
    Ye, Hongbo
    Hu, Shaojian
    Ren, Zheng
    ISAPE 2008: THE 8TH INTERNATIONAL SYMPOSIUM ON ANTENNAS, PROPAGATION AND EM THEORY, PROCEEDINGS, VOLS 1-3, 2008, : 1023 - +
  • [10] Extraction and applications of on-chip interconnect inductance
    Wong, SS
    Kim, SY
    Yue, CP
    Chang, R
    O'Mahony, F
    2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 142 - 146