A low noise, 2.0 GHz CMOS VCO design

被引：0

作者：

Cheng, KH

Kuo, SC

Tu, CM

机构：

来源：

PROCEEDINGS OF THE 46TH IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS & SYSTEMS, VOLS 1-3 | 2003年

关键词：

voltage-controlled oscillator; operating frequencies; phase noise; power supply noise;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a new delay cell of the voltage-controlled oscillator (VCO) is proposed The new circuit is designed and fabricated in TSMC 0.25um 1p5m CMOS process with a 2.5 V supply voltage. It utilizes the skill that decreases the transient time to achieve the wider operating frequencies, lower phase noise and lower power supply noise. The structure of the VCO is implemented in the dual-delay path techniques. The simulation result of the operation frequency range is 0.85 similar to 2.1 GHz and the power consumption of the maximum oscillation frequency is 12 m W.

引用

页码：205 / 208

页数：4

共 5 条

[1] Cheng KH, 2002, 2002 IEEE ASIA-PACIFIC CONFERENCE ON ASIC PROCEEDINGS, P263, DOI 10.1109/APASIC.2002.1031582
[2] HAN YC, 2001, IEEE S MIDW, V1, P324
[3] Lee SJ, 1997, IEEE J SOLID-ST CIRC, V32, P289, DOI 10.1109/4.551926
[4] Path selection and pattern generation for dynamic timing analysis considering power supply noise effects
Liou, JJ
Krstic, A
Jiang, YM
Cheng, KT
[J]. ICCAD - 2000 : IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, 2000, : 493 - 496
[5] A low-noise, 900-MHz VCO in 0.6-μm CMOS
Park, CH
Kim, B
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (05) : 586 - 591

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