A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp Third-Order ΣΔ Modulator

被引：24
作者：
Pena-Perez, Aldo [1 ]
Bonizzoni, Edoardo [1 ]
Maloberti, Franco [1 ]
机构：
[1] Univ Pavia, Dept Elect, I-27100 Pavia, Italy
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2012年 / 47卷 / 09期
关键词：
Analog-digital conversion; mixed analog-digital integrated circuits; noise shaping; operational amplifier; sigma-delta (Sigma Delta) modulation; switched-capacitor circuits; ADC; DB;
D O I：
10.1109/JSSC.2012.2199669
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A low-power switched-capacitor third-order sigma-delta (Sigma Delta) modulator suitable for portable sensor systems is described. The architecture uses only one operational amplifier working in a time-interleaved fashion. The architecture employs swing reduction techniques to limit the swing and the slew-rate requirements of all internal nodes. Realized in a 0.18-mu m 2P6M CMOS technology, the modulator provides 84-dB SNDR and 88-dB dynamic range in a signal bandwidth of 100 kHz and clock at 3.2 MHz. The 1.5-V supplied prototype dissipates 140 mu W with a FoM of 54 fJ/conversion-level.
引用
收藏
页码：2107 / 2118
页数：12
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