Challenges and Limitations of NAND Flash Memory Devices Based on Floating Gates

被引：0

作者：

Park, Byoungjun ^{[1
]}

Cho, Sunghoon ^{[1
]}

Park, Milim ^{[1
]}

Park, Sukkwang ^{[1
]}

Lee, Yunbong ^{[1
]}

Cho, Myoung Kwan ^{[1
]}

Ahn, Kun-Ok ^{[1
]}

Bae, Gihyun ^{[1
]}

Park, Sungwook ^{[1
]}

机构：

[1] Hynix Semicond Inc, Flash Dev Div, 55 Hyangjeong Dong, Chonju 361725, South Korea

来源：

2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012) | 2012年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, the limitations and challenges of NAND flash memory devices based on floating gates are discussed. And, the newly adopted operation algorithms, such as intelligent incremental step pulse erase, various biasing in grouped W/Ls, virtual negative read and data randomization, and their results are exhibited.

引用

页码：420 / 423

页数：4

共 9 条

[1]

Bauer M., 1995, IEEE ISSCC FEBR A, VA247, P132

[2] Improvement of Interpoly Dielectric Characteristics by Plasma Nitridation and Oxidation for Future NAND Flash Memory [J].

Ho, Ching Yuan ;

Lien, Chenhsin ;

Sakamoto, Y. ;

Yang, Ru Jye ;

Fijita, Hiro ;

Liu, C. H. ;

Lin, Y. M. ;

Pittikoun, S. ;

Aritome, S. .

IEEE ELECTRON DEVICE LETTERS, 2008, 29 (11) :1199-1202

[3]

Kinam Kim, 2006, 21st Non-Volatile Semiconductor Memory Workshop. (IEEE Cat. No. 06EX1246), P9, DOI 10.1109/.2006.1629474

[4] A 32-Gb MLC NAND Flash Memory With Vth Endurance Enhancing Schemes in 32 nm CMOS [J].

Lee, Changhyuk ;

Lee, Sok-Kyu ;

Ahn, Sunghoon ;

Lee, Jinhaeng ;

Park, Wonsun ;

Cho, Yongdeok ;

Jang, Chaekyu ;

Yang, Chulwoo ;

Chung, Sanghwa ;

Yun, In-Suk ;

Joo, Byoungin ;

Jeong, Byoungkwan ;

Kim, Jeeyul ;

Kwon, Jeakwan ;

Jin, Hyunjong ;

Noh, Yujong ;

Ha, Jooyun ;

Sung, Moonsoo ;

Choi, Daeil ;

Kim, Sanghwan ;

Choi, Jeawon ;

Jeon, Taeho ;

Park, Heejoung ;

Yang, Joong-Seob ;

Koh, Yo-Hwan .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (01) :97-106

[5]

Lee D. W., 2010, FLASH MEM SUMM

[6]

Lee Y., 2010, P INT MEM WORKSH

[7]

Lue H.-T., 2010, S VLSI, P123

[8] A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories [J].

Park, Ki-Tae ;

Kang, Myounggon ;

Kim, Doogon ;

Hwang, Soon-Wook ;

Choi, Byung Yong ;

Lee, Yeong-Taek ;

Kim, Changhyun ;

Kim, Kinam .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (04) :919-928

[9]

Shin YS, 2005, 2005 Symposium on VLSI Circuits, Digest of Technical Papers, P156

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