A 5 MHz integrated digital DC-DC converter with a delay-line ADC and a Σ-Δ DPWM

被引:2
作者
Wang, Hongyi [1 ]
Hu, Xi [1 ]
Wang, Shizhen [1 ]
Zhao, Gangdong [1 ]
Luo, Dongzhe [1 ]
机构
[1] Xi An Jiao Tong Univ, Dept Elect & Informat Engn, Xian 710049, Peoples R China
来源
IEICE ELECTRONICS EXPRESS | 2013年 / 10卷 / 06期
关键词
DC-DC converter; digital PID control; delay-line ADC; Sigma-Delta modulator; DLL; CONTROLLER; PWM;
D O I
10.1587/elex.10.20130124
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An integrated digital buck DC-DC converter based on a 0.5 mu m standard CMOS process is presented in this paper. Its switching frequency is 5 MHZ and no extra high frequency clock is needed. The delay-line ADC with a self-calibration loop utilized in the converter has low sensitivity to the process, voltage, temperature and loading (PVTL). The DPWM in the proposed DC-DC converter employs a first-order Sigma-Delta modulator to achieve an equivalent resolution of 10-bit. The simulation results show that the proposed DC-DC converter can operate at the supply voltage range of 2.7 to 3.6 V with a transient response time of 30 mu s. The peak efficiency reaches 94%.
引用
收藏
页数:12
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