High performance double-gate device technology challenges and opportunities

被引：25

作者：

Ieong, M ^{[1
]}

Wong, HSP ^{[1
]}

Nowak, E ^{[1
]}

Kedzierski, J ^{[1
]}

Jones, EC ^{[1
]}

机构：

[1] IBM Corp, Microelect Semicond Res & Dev Ctr SRDC, Hopewell Jct, NY 12533 USA

来源：

PROCEEDING OF THE 2002 3RD INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN | 2002年

关键词：

D O I：

10.1109/ISQED.2002.996793

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The double-gate FET is widely recognized as the prime candidate for the ultimate scaling of FET to the shortest channel length. In the device integration point of view, the attainment of low extrinsic resistance, carrier transport in double-gated thin silicon channel, and threshold voltages control remained a significant obstacle to high-performance double-gate CMOS structures. We report how these issues were addressed to achieve world-record double-gate device performance. The second gate in a double-gate device can be utilized for low-power and mixed-signal applications. The flexibility of individually controlling the two gates provides opportunities for overall system performance improvement. Ultra-low voltage operation of double-gate CMOS inverters was demonstrated. Finally, we will discuss the migration of existing circuit/layout designs to double-gate device technology.

引用

页码：492 / 495

页数：4