Design of Ultra-Low-Power 60-GHz Direct-Conversion Receivers in 65-nm CMOS

被引:20
作者
Cai, Deyun [1 ]
Shang, Yang [1 ]
Yu, Hao [1 ]
Ren, Junyan [2 ]
机构
[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore
[2] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China
关键词
CMOS; 65; nm; direct-conversion receiver; quadrature hybrid coupler; 60; GHz; ultra-low power; LIMITING AMPLIFIER; TRANSCEIVER; OSCILLATOR; RESONATOR;
D O I
10.1109/TMTT.2013.2268738
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper has explored an ultra-low-power design of two 60-GHz direct-conversion receivers in a 65-nm CMOS process for single-channel and multi-channel applications under the IEEE 802.15.3c standard, respectively. One subthreshold biasing 0.4-V transconductance mixer is designed with a compact quadrature hybrid coupler (160 mu m x 210 mu m with measured 3-dB intrinsic loss) in receivers to achieve low power (8 mW for single channel and 12.4 mW for multi-channel) and high gain (55 dB for single channel and 62-dB for multi-channel). One three-stage low-noise amplifier employs high-Q passive matchings. A double-layer-stacked inductor is utilized for matching in the single-channel receiver and a high-impedance transmission line is utilized for matching in the multi-channel receiver, respectively. In addition, one new modified Cherry-Hooper amplifier is applied for the variable-gain amplifier design to achieve high gain-bandwidth product and high power efficiency. The single-channel receiver is implemented with 0.34-mm(2) chip area. It is measured with a power consumption of 8 mW, a minimum single-sideband noise figure (NF) of 4.9 dB, a 3-dB bandwidth of 3.5 GHz, and a maximum conversion gain of 55 dB. The multi-channel receiver is implemented with 0.56-mm(2) chip area. It is measured with a power consumption of 12.4 mW, a 3-dB bandwidth of 8 GHz (59.5 similar to 67.5 GHz), and a maximum conversion gain of 62 dB. The measurement results show that the two demonstrated 60-GHz direct-conversion receivers can achieve high gain and low NF with ultra-low power in 65-nm CMOS.
引用
收藏
页码:3360 / 3372
页数:13
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