Comparative Analysis of Harmonic Reduction in Multilevel Inverter

被引：0
|
作者：
Karnik, Neha [1 ]
Singla, Deepshikha [1 ]
Sharma, P. R. [2 ]
机构：
[1] MRIU, Elect & Elect Engn, Faridabad, Haryana, India
[2] YMCAUST, Elect & Elect Engn, Faridabad, India
来源：
2012 IEEE FIFTH POWER INDIA CONFERENCE | 2012年
关键词：
Cascaded Multilevel Inverter; Harmonics; Multilevel Inverters; Power Quality; Pulse Width Modulation (PWM); ELIMINATION PWM; CONVERTERS; TOPOLOGIES; STATCOM;
D O I：
暂无
中图分类号：
TE [石油、天然气工业]; TK [能源与动力工程];
学科分类号：
0807 ; 0820 ;
摘要：
In this paper, different multilevel inverter topologies and their comparison has been presented. Multilevel inverter topologies (MLIs) are increasingly being used in medium and high power applications due to their many advantages such as low power dissipation on power switches, low harmonic contents and low electromagnetic interference (EMI) outputs. The distortion of the output voltage decreases as the number of level increases and it is further improved by applying pulse width modulation (PWM) techniques. In this work, an attempt has been made to reduce the harmonic content in the output voltage by incorporating different multi level inverter topologies using sinusoidal PWM technique. The gating signals for the switches are generated with the help of the switching table and the power circuit is simulated in MATLAB/Simulink.
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页数：5
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