Back-off efficiency;
CMOS technology;
Doherty power amplifier;
series combining transformer;
DISTRIBUTED ACTIVE-TRANSFORMER;
AMPLIFIER;
CMOS;
D O I:
10.1109/TCSI.2012.2221223
中图分类号:
TM [电工技术];
TN [电子技术、通信技术];
学科分类号:
0808 ;
0809 ;
摘要:
This paper analyzes the back-off efficiency enhancement characteristics of transformer combined power amplifiers taking into account the amplifier and transformer parasitics. The dynamic power combining properties of different transformer architectures are investigated. The co-optimization of the transformer and the amplifiers is presented for the transformer-based Doherty power amplifier which is a linear class of operation with back-off efficiency enhancement. Then this analysis is extended for the uneven Doherty power amplifier which employs asymmetrical transformers. The proposed design methodology is used to design a 2.4 GHz uneven Doherty power amplifier in standard 90 nm CMOS technology. The fabricated two stage Doherty amplifier achieves 26.2 dBm peak output power at 2 V supply. The measured peak drain efficiency of the PA is 37% while the efficiency at 6 dB back-off is still as high as 30.1%.
引用
收藏
页码:825 / 835
页数:11
相关论文
共 13 条
[11]
Wei Tai, 2011, 37th European Solid State Circuits Conference (ESSCIRC 2011), P131, DOI 10.1109/ESSCIRC.2011.6044882